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    Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation
    2.
    发明授权
    Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation 有权
    计算机系统包括存储器操作的优先级，并允许较高优先级的存储器操作来中断较低优先级的存储器操作

    公开(公告)号：US06298424B1

    公开(公告)日：2001-10-02

    申请号：US09522649

    申请日：2000-03-10

    申请人： W. Kurt Lewchuk ,  Brian D. McMinn ,  James K. Pickett

    发明人： W. Kurt Lewchuk ,  Brian D. McMinn ,  James K. Pickett

    IPC分类号： G06F1318

    CPC分类号： G06F13/18

    摘要： A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch priority level and a prefetch priority level. The fetch priority level is higher priority than the prefetch priority level, and is assigned to memory operations which are the direct result of executing an instruction. The prefetch priority level is assigned to memory operations which are generated according to a prefetch algorithm implemented by the microprocessor. As memory operations are routed through the computer system to main memory and corresponding data transmitted, the elements involved in performing the memory operations are configured to interrupt the transfer of data for the lower priority memory operation in order to perform the data transfer for the higher priority memory operation. While one embodiment of the computer system employs at least a fetch priority and a prefetch priority, the concept of applying priority levels to various memory operations and interrupting data transfers of lower priority memory operations to higher priority memory operations may be extended to other types of memory operations, even if prefetching is not employed within a computer system. For example, speculative memory operations may be prioritized lower than non-speculative memory operations throughout the computer system.

    摘要翻译： 计算机系统包括一个或多个微处理器。 微处理器在启动存储器操作时为每个存储器操作分配一个优先级。 在一个实施例中，微处理器采用的优先级包括提取优先级和预取优先级。 提取优先级高于预取优先级，并被分配给作为执行指令的直接结果的存储器操作。 预取优先级被分配给根据由微处理器实现的预取算法生成的存储器操作。 由于存储器操作通过计算机系统被路由到主存储器和相应的数据传输，执行存储器操作所涉及的元件被配置为中断低优先级存储器操作的数据传输，以执行更高优先级的数据传输 内存操作。 虽然计算机系统的一个实施例至少采用取出优先级和预取优先级，但是将优先权等级应用于各种存储器操作和中断低优先级存储器操作的数据传输到较高优先级存储器操作的概念可以扩展到其他类型的存储器 操作，即使在计算机系统内不使用预取。 例如，在整个计算机系统中，推测性存储器操作的优先级低于非推测性存储器操作。

    Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation
    3.
    发明授权
    Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation 失效
    计算机系统包括存储器操作的优先级，并允许较高优先级的存储器操作中断较低优先级的存储器操作

    公开(公告)号：US6058461A

    公开(公告)日：2000-05-02

    申请号：US982588

    申请日：1997-12-02

    申请人： W. Kurt Lewchuk ,  Brian D. McMinn ,  James K. Pickett

    发明人： W. Kurt Lewchuk ,  Brian D. McMinn ,  James K. Pickett

    IPC分类号： G06F13/18

    CPC分类号： G06F13/18

    摘要： A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch priority level and a prefetch priority level. The fetch priority level is higher priority than the prefetch priority level, and is assigned to memory operations which are the direct result of executing an instruction. The prefetch priority level is assigned to memory operations which are generated according to a prefetch algorithm implemented by the microprocessor. As memory operations are routed through the computer system to main memory and corresponding data transmitted, the elements involved in performing the memory operations are configured to interrupt the transfer of data for the lower priority memory operation in order to perform the data transfer for the higher priority memory operation. While one embodiment of the computer system employs at least a fetch priority and a prefetch priority, the concept of applying priority levels to various memory operations and interrupting data transfers of lower priority memory operations to higher priority memory operations may be extended to other types of memory operations, even if prefetching is not employed within a computer system. For example, speculative memory operations may be prioritized lower than non-speculative memory operations throughout the computer system.

    摘要翻译： 计算机系统包括一个或多个微处理器。 微处理器在启动存储器操作时为每个存储器操作分配一个优先级。 在一个实施例中，微处理器采用的优先级包括提取优先级和预取优先级。 提取优先级高于预取优先级，并被分配给作为执行指令的直接结果的存储器操作。 预取优先级被分配给根据由微处理器实现的预取算法生成的存储器操作。 由于存储器操作通过计算机系统被路由到主存储器和相应的数据传输，执行存储器操作所涉及的元件被配置为中断低优先级存储器操作的数据传输，以执行更高优先级的数据传输 内存操作。 虽然计算机系统的一个实施例至少采用取出优先级和预取优先级，但是将优先权等级应用于各种存储器操作和中断低优先级存储器操作的数据传输到较高优先级存储器操作的概念可以扩展到其他类型的存储器 操作，即使在计算机系统内不使用预取。 例如，在整个计算机系统中，推测性存储器操作的优先级低于非推测性存储器操作。

    Prefetching data using profile of cache misses from earlier code executions
    4.
    发明授权
    Prefetching data using profile of cache misses from earlier code executions 失效
    使用早期代码执行的高速缓存未命中配置文件预取数据

    公开(公告)号：US6047363A

    公开(公告)日：2000-04-04

    申请号：US950337

    申请日：1997-10-14

    申请人： W. Kurt Lewchuk

    发明人： W. Kurt Lewchuk

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F2212/6024

    摘要： During execution of a code sequence, a profile is generated containing addresses of the data cache misses experienced during the execution. The profile is associated with the code sequence such that, during a future execution of the code sequence, the profile is available. Prefetching may be performed, based on the profile. Since the profile records a sequence of miss addresses, an arbitrarily complex miss pattern can be prefetched. In one embodiment, multiple profiles may be associated with a code sequence having multiple entry points (e.g. multiple instructions at which execution may begin within the code sequence). When the code sequence is executed, the profile associated with the entry point of the current execution may be selected. Additionally, a new profile may be generated. If the entry point of the current execution is not associated with a profile, the new profile is saved. If the entry point of the current execution is associated with a profile, the new profile is saved if the current profile is found to be ineffective.

    摘要翻译： 在执行代码序列期间，生成包含在执行期间经历的数据高速缓存未命中的地址的简档。 配置文件与代码序列相关联，使得在将来执行代码序列期间，配置文件可用。 可以基于简档来执行预取。 由于配置文件记录了未命中的地址序列，因此可以预取任意复杂的丢失模式。 在一个实施例中，多个简档可以与具有多个入口点的代码序列相关联（例如，可以在代码序列内开始执行的多个指令）。 当执行代码序列时，可以选择与当前执行的入口点相关联的简档。 另外，可能会生成新的配置文件。 如果当前执行的入口点与配置文件没有关联，则保存新配置文件。 如果当前执行的入口点与配置文件相关联，则如果发现当前配置文件无效，则会保存新配置文件。

    Prefetching data using profile of cache misses from earlier code executions
    5.
    发明授权
    Prefetching data using profile of cache misses from earlier code executions 失效

    公开(公告)号：US6157993A

    公开(公告)日：2000-12-05

    申请号：US476938

    申请日：2000-01-03

    申请人： W. Kurt Lewchuk

    发明人： W. Kurt Lewchuk

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0862 ,  G06F2212/6024

    摘要： During execution of a code sequence, a profile is generated containing addresses of the data cache misses experienced during the execution. The profile is associated with the code sequence such that, during a future execution of the code sequence, the profile is available. Prefetching may be performed, based on the profile. Since the profile records a sequence of miss addresses, an arbitrarily complex miss pattern can be prefetched. In one embodiment, multiple profiles may be associated with a code sequence having multiple entry points (e.g. multiple instructions at which execution may begin within the code sequence). When the code sequence is executed, the profile associated with the entry point of the current execution may be selected. Additionally, a new profile may be generated. If the entry point of the current execution is not associated with a profile, the new profile is saved. If the entry point of the current execution is associated with a profile, the new profile is saved if the current profile is found to be ineffective.

    Dataless touch to open a memory page
    7.
    发明授权
    Dataless touch to open a memory page 失效
    无数触摸打开记忆页面

    公开(公告)号：US5983325A

    公开(公告)日：1999-11-09

    申请号：US987536

    申请日：1997-12-09

    申请人： W. Kurt Lewchuk

    发明人： W. Kurt Lewchuk

    IPC分类号： G06F9/38 ,  G06F12/02 ,  G06F12/08

    CPC分类号： G06F12/0802 ,  G06F12/0215 ,  G06F9/383

    摘要： A computer system supports a touch command which may be used to open a page in the main memory. Microprocessors within the computer system may determine an appropriate time at which to perform the touch command, and then transmit the touch command to the memory controller within the computer system. In response to the touch command, the memory controller opens the selected page but may not return data from the page. Subsequent memory operations may experience a page hit memory latency instead of a page miss memory latency due to the occurrence of the touch command. Data bus bandwidth is not consumed by the touch command. The touch command may be used even if actually prefetching data is not desirable. The microprocessors in the computer system may monitor which pages are experiencing cache hits within the microprocessors. If a page is experiencing cache hits, a cache miss within the page may be more probable. The touch command may be used to prepare the main memory system for a potential cache miss.

    摘要翻译： 计算机系统支持可用于打开主存储器中的页面的触摸命令。 计算机系统内的微处理器可以确定执行触摸命令的适当时间，然后将触摸命令发送到计算机系统内的存储器控​​制器。 响应于触摸命令，存储器控制器打开所选择的页面，但不能从页面返回数据。 由于触摸命令的发生，随后的存储器操作可能经历页面命中存储器延迟而不是页错过存储器延迟。 触摸命令不会消耗数据总线带宽。 即使不希望实际预取数据，也可以使用触摸命令。 计算机系统中的微处理器可以监视微处理器中哪些页面正在经历高速缓存命中。 如果页面正在经历缓存命中，则页面中的高速缓存未命中可能更可能。 触摸命令可用于准备主存储器系统以用于潜在的高速缓存未命中。

    Branch prediction unit which approximates a larger number of branch predictions using a smaller number of branch predictions and an alternate target indication
    8.
    发明授权
    Branch prediction unit which approximates a larger number of branch predictions using a smaller number of branch predictions and an alternate target indication 失效
    分支预测单元，其使用更少数量的分支预测和替代目标指示来近似更大数量的分支预测

    公开(公告)号：US5974542A

    公开(公告)日：1999-10-26

    申请号：US960818

    申请日：1997-10-30

    申请人： Chinh N. Tran ,  W. Kurt Lewchuk

    发明人： Chinh N. Tran ,  W. Kurt Lewchuk

    IPC分类号： G06F9/38 ,  G06F9/40

    CPC分类号： G06F9/3806 ,  G06F9/3844

    摘要： A branch prediction unit includes a cache-line based branch prediction storage having a branch prediction storage location assigned to each cache line of an instruction cache within the microprocessor employing the branch prediction unit. Although each branch prediction storage location is assigned to a particular cache line, the branch prediction storage location stores an alternate target indication indicating whether a branch prediction within the storage location corresponds to a branch instruction within the cache line to which the storage location is assigned or to a branch instruction within a different cache line. The different cache line has a predetermined relationship to the cache line to which the storage location is assigned. In various embodiments, the different cache line is at an index one less than the index of the storage location or is within a different way of the same index. The branch prediction unit described herein approximates having multiple branch predictions per cache line even though only one branch prediction storage location is assigned to the cache line. In cases in which a branch prediction would have been unused due to a lack of sufficient predicted-taken branch instructions within a cache line, the unused branch prediction may be used by a different cache line having a large number of branch instructions.

    摘要翻译： 分支预测单元包括基于高速缓存行的分支预测存储器，其具有分配给使用分支预测单元的微处理器内的指令高速缓存行的每个高速缓存行的分支预测存储位置。 虽然分支预测存储位置被分配给特定的高速缓存行，但是分支预测存储位置存储指示存储位置内的分支预测是否对应于分配存储位置的高速缓存行内的分支指令的替代目标指示，或者 到不同高速缓存行中的分支指令。 不同的高速缓存行与分配存储位置的高速缓存线具有预定的关系。 在各种实施例中，不同的高速缓存线的索引值小于存储位置的索引，或者处于相同索引的不同方式。 即使只有一个分支预测存储位置被分配给高速缓存线，这里描述的分支预测单元近似于每个高速缓存行具有多个分支预测。 在由于在高速缓存线内缺少足够的预测分支指令而不能使用分支预测的情况下，未使用的分支预测可以由具有大量分支指令的不同高速缓存线路使用。