公开(公告)号：US06694427B1

公开(公告)日：2004-02-17

申请号：US09552859

申请日：2000-04-20

申请人： Alexander Erik Mericas ,  William John Starke ,  Joel M. Tendler

发明人： Alexander Erik Mericas ,  William John Starke ,  Joel M. Tendler

IPC分类号： G06F900

CPC分类号： G06F9/3863 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3842 ,  G06F11/3636

摘要： A method, system and apparatus for instruction tracing with out of order speculative processors. With the present invention, information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions fetched by the processor. When a cache load is necessary, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during fetching of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions fetched is known from the fetched instructions information stored in the trace storage device. Hence the instruction stream may be reconstructed from the information stored in the trace storage device.

摘要翻译： 用于无序推测处理器的指令跟踪的方法，系统和装置。 利用本发明，与指令高速缓存和数据高速缓存的状态相对应的信息与对应于由处理器获取的指令的信息一起存储在跟踪存储设备中。 当需要缓存加载时，更新的缓存信息被存储在跟踪存储设备中。 因此，可以从存储在跟踪存储装置中的信息中知道在取指令期间的任何时候的高速缓存的状态。 此外，从存储在跟踪存储设备中的获取的指令信息中可以获得所提取的特定指令。 因此，可以从存储在跟踪存储设备中的信息重建指令流。

公开(公告)号：US06748522B1

公开(公告)日：2004-06-08

申请号：US09703346

申请日：2000-10-31

申请人： Dennis Gerard Gregoire ,  Alexander Erik Mericas ,  Joel M. Tendler

发明人： Dennis Gerard Gregoire ,  Alexander Erik Mericas ,  Joel M. Tendler

IPC分类号： G06F1130

CPC分类号： G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

摘要： The problem identified above is addressed in large part by a microprocessor as disclosed herein. The microprocessor includes a dispatch unit configured to receive a set of instructions from an instruction cache and to forward the set of instructions to an issue queue when the instructions are ready for execution. The dispatch unit may include sampling logic that is configured to select one of the instructions for performance monitoring from the set of instructions. The microprocessor further includes a performance monitor unit enabled to monitor performance characteristics of the selected instruction as it executes. The sampling logic may identify the instruction selected for monitoring as the instruction occupying an eligible position within the set of instructions. The eligible position from which the monitored instruction is selected may vary with each subsequent set of instructions. The sampling logic may include a selection mask that contains an asserted bit that identifies the position within the set of instructions from which the selected instruction is chosen. The selection mask may include a single bit for each position in the set of instructions and may be implemented as a shift register that periodically rotates the eligible position. The rotation of the eligible bit position may occur every clock cycle, every dispatch cycle, or at some another suitable synchronous or asynchronous interval. The selection mask may contain multiple asserted bits and may include a filter circuit that generates a selection vector based on the selection mask where the selection vector includes only a single asserted bit.

摘要翻译： 上述问题在很大程度上由本文公开的微处理器来解决。 微处理器包括配置单元，配置为从指令高速缓存接收一组指令，并且当指令准备好执行时将指令集转发到发行队列。 调度单元可以包括采样逻辑，其被配置为从该组指令中选择用于性能监视的指令之一。 微处理器还包括一个性能监视器单元，能够在执行时监视所选指令的性能特征。 采样逻辑可以将所选择的用于监视的指令识别为在该组指令内占据合格位置的指令。 所选择的被监视指令的合格位置可随随后的指令集而变化。 采样逻辑可以包括选择掩码，其包含标识位于所选择的指令所选择的指令集内的位置的有效位。 选择掩模可以包括指令集中的每个位置的单个位，并且可以被实现为周期性地旋转合格位置的移位寄存器。 合格位位置的旋转可以在每个时钟周期，每个调度周期或在另一个合适的同步或异步间隔中发生。 选择掩码可以包含多个被断言的位，并且可以包括滤波器电路，该滤波器电路基于选择矢量生成选择向量，其中选择向量仅包括单个被断言位。

公开(公告)号：US06539500B1

公开(公告)日：2003-03-25

申请号：US09428410

申请日：1999-10-28

申请人： James Allan Kahle ,  Alexander Erik Mericas ,  Kevin Franklin Reick ,  Joel M. Tendler

发明人： James Allan Kahle ,  Alexander Erik Mericas ,  Kevin Franklin Reick ,  Joel M. Tendler

IPC分类号： G06F1100

CPC分类号： G06F11/3636

摘要： The present invention discloses a system and method for implementing instruction tracing in a computer system and in particular a computer system with a tightly coupled shared processor central processor unit (CPU). Each of the processors are generally purpose processors that have been modified by design to allow an instruction to execute and simultaneously to be stored and forwarded to shared memory operable as a trace buffer. Since each processor is general purpose, the trace routine necessary for tracing, can by one of the routines or programs that can be written and executed on either of the processors. One of the processors can run, collect and analyze the executed and store instructions of the other processor. Since the processors can be on a single chip the shared memory bus that writes and reads the executed instructions can operate at high speed. Also since the trace function is part of the multiprocessor architecture its speed of operation will scale with the speed of the processors without modification.

摘要翻译： 本发明公开了一种用于在计算机系统中实现指令跟踪的系统和方法，特别是具有紧耦合的共享处理器中央处理器单元（CPU）的计算机系统。 每个处理器通常是通过设计修改的目的处理器，以允许指令执行并同时被存储并转发到可用作跟踪缓冲器的共享存储器。 由于每个处理器是通用目的，因此可以通过其中一个可以在任一处理器上编写和执行的程序之一进行跟踪所需的跟踪例程。 其中一个处理器可以运行，收集和分析其他处理器的执行和存储指令。 由于处理器可以在单个芯片上，写入和读取执行的指令的共享存储器总线可以高速运行。 此外，由于跟踪功能是多处理器架构的一部分，因此操作速度将随着处理器的速度而不变化。

公开(公告)号：US06415378B1

公开(公告)日：2002-07-02

申请号：US09343359

申请日：1999-06-30

申请人： Joel Roger Davidson ,  Judith K. Laurens ,  Alexander Erik Mericas ,  Kevin F. Reick ,  Joel M. Tendler

发明人： Joel Roger Davidson ,  Judith K. Laurens ,  Alexander Erik Mericas ,  Kevin F. Reick ,  Joel M. Tendler

IPC分类号： G06F1100

CPC分类号： G06F11/3466

摘要： A method and system for debugging the execution of an instruction within an instruction pipeline is provided. A processor in a data processing system contains instruction pipeline units. An instruction may be tagged, and in response to an instruction pipeline unit completing its processing of the tagged instruction, a stage completion signal is asserted. An execution monitor external to the pipelined processor monitors the stage completion signals during the execution of the tagged instruction. The execution monitor may be a logic analyzer that displays the stage completion signals in real-time on a display device of the execution monitor. An instruction to be tagged may be selected based upon an instruction selection rule, such as the address of the instruction.

摘要翻译： 提供了一种用于调试指令管线内的指令执行的方法和系统。 数据处理系统中的处理器包含指令流水线单元。 指令可以被标记，并且响应于指令流水线单元完成其对带标签的指令的处理，声明级完成信号。 流水线处理器外部的执行监视器在执行标记指令期间监视阶段完成信号。 执行监视器可以是在执行监视器的显示装置上实时显示级完成信号的逻辑分析器。 可以基于诸如指令的地址的指令选择规则来选择要被标记的指令。

公开(公告)号：US06574712B1

公开(公告)日：2003-06-03

申请号：US09550180

申请日：2000-04-14

申请人： James Allan Kahle ,  Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray ,  Edward John Silha ,  Joel M. Tendler

发明人： James Allan Kahle ,  Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray ,  Edward John Silha ,  Joel M. Tendler

IPC分类号： G06F1208

CPC分类号： G06F9/383 ,  G06F9/30047 ,  G06F9/3802 ,  G06F12/0862 ,  G06F12/0897 ,  G06F2212/6028

摘要： A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction is used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine. The instruction also limits the amount of data to be prefetched.

摘要翻译： 数据处理系统包括具有第一级高速缓存和预取引擎的处理器。 耦合到处理器的是二级缓存和第三级缓存和系统存储器。 通过预取引擎对高速缓存行的预取执行到第一，第二和第三级高速缓存中的每一个。 从预取引擎到第二和第三级高速缓存的预取请求通过专用预取请求总线执行，该专用预取请求总线与将数据从各种高速缓存级别传送到处理器的总线系统分开。 软件指令用于通过覆盖硬件预取引擎的正常功能来加速预取过程。 该指令还限制了要预取的数据量。