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1.发明授权公开(公告)号：US07649538B1
公开(公告)日：2010-01-19
申请号：US11556674
申请日：2006-11-03
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donovan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donovan , Emmett M. Kilgariff
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译： 提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。 一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。 对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。 当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。
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2.发明授权公开(公告)号：US07884831B2
公开(公告)日：2011-02-08
申请号：US12689939
申请日：2010-01-19
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J. M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译： 提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。 一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。 对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。 当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。
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3.发明申请公开(公告)号：US20100118043A1
公开(公告)日：2010-05-13
申请号：US12689939
申请日：2010-01-19
申请人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J.M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
发明人： Alexander L. Minkin , Joel J. McCormack , Paul S. Heckbert , Michael J.M. Toksvig , Luke Y. Chang , Karim Abdalla , Bo Hong , John W. Berendsen , Walter Donavan , Emmett M. Kilgariff
IPC分类号： G09G5/00
CPC分类号： G06T1/60 , G06F3/14 , G06T15/04 , G06T2200/28 , G09G5/026 , G09G5/22 , G09G5/363 , G09G5/393 , G09G5/395 , G09G2360/06 , G09G2360/121 , G09G2360/18
摘要： Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要翻译： 提供纹理缓存和相关电路的电路，方法和装置，以快速和有效的方式存储和检索纹素。 一个这样的纹理电路为一组像素中的每个像素提供了更多数量的iler骨，特别是当需要三线性或茴香过滤时。 对于三线性滤波，在一个时钟周期内针对多个像素检索第一和第二细节级别的纹素。 当执行了茴香过滤时，可以在一个时钟周期内为多个像素中的每一个检索多个b骨。
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4.发明授权System and method using a packetized encoded bitstream for parallel compression and decompression 失效使用分组编码比特流进行并行压缩和解压缩的系统和方法公开(公告)号：US06862278B1
公开(公告)日：2005-03-01
申请号：US09099742
申请日：1998-06-18
CPC分类号： H04N19/436 , H04N19/176 , H04N19/186 , H04N19/60
摘要： A system and method are disclosed for parallel compression and decompression of a bitstream. For compression, the bitstream is separated into a plurality of components, and the components are encoded using a compression algorithm. Packets are then constructed from the encoded components. At least one packet is associated with each encoded component and comprises header information and encoded data. The packets are combined into a packetized encoded bitstream. For decompression, the packets are separated from the packetized encoded bitstream using the header information. The packets are then decoded in parallel using a decompression algorithm to recover the encoded data. The plurality of components are reconstructed from the recovered encoded data and combined to recover the bitstream.
摘要翻译： 公开了用于比特流的并行压缩和解压缩的系统和方法。 为了压缩，将比特流分成多个组件，并且使用压缩算法对组件进行编码。 然后从编码的组件构建包。 至少一个分组与每个编码的分量相关联并且包括报头信息和编码数据。 分组被组合成分组化的编码比特流。 对于解压缩，使用报头信息将分组与分组化的编码比特流分离。 然后使用解压缩算法并行解码分组以恢复编码数据。 从恢复的编码数据重建多个分量，并组合以恢复比特流。
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公开(公告)号：US07479965B1
公开(公告)日：2009-01-20
申请号：US11105198
申请日：2005-04-12
CPC分类号： G09G5/393 , G06T15/503 , G06T2200/12 , G09G5/363 , G09G2340/02 , G09G2340/10 , G09G2360/122
摘要： Circuits, methods, and apparatus that reduce the amount of data transferred between a graphics processor integrated circuit and graphics memory. Various embodiments of the present invention further improve the efficiency of blenders that are included on a graphics processor. One embodiment provides for the storage of a reduced number of subsamples of a pixel when the storage of a larger number of subsamples would be redundant. The number of subsamples that are blended with source data are compressed, thereby reducing the task load on the blenders increasing their efficiency. These methods can be disabled to avoid errors that may arise in certain applications.
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公开(公告)号：US07629982B1
公开(公告)日：2009-12-08
申请号：US12332366
申请日：2008-12-11
CPC分类号： G09G5/393 , G06T15/503 , G06T2200/12 , G09G5/363 , G09G2340/02 , G09G2340/10 , G09G2360/122
摘要： Circuits, methods, and apparatus that reduce the amount of data transferred between a graphics processor integrated circuit and graphics memory. Various embodiments of the present invention further improve the efficiency of blenders that are included on a graphics processor. One embodiment provides for the storage of a reduced number of subsamples of a pixel when the storage of a larger number of subsamples would be redundant. The number of subsamples that are blended with source data are compressed, thereby reducing the task load on the blenders increasing their efficiency. These methods can be disabled to avoid errors that may arise in certain applications.
摘要翻译： 降低在图形处理器集成电路和图形存储器之间传送的数据量的电路，方法和装置。 本发明的各种实施例进一步提高包括在图形处理器中的搅拌机的效率。 当更大数量的子样本的存储将是冗余时，一个实施例提供了减少数量的像素子样本的存储。 与源数据混合的子样本的数量被压缩，从而减少了混合器上的任务负担，提高了它们的效率。 可以禁用这些方法，以避免某些应用中可能出现的错误。
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