摘要:
Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要:
Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.
摘要:
A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.
摘要:
A method for implementing LOD (level of detail) filtering in a cube mapping application. The method includes accessing a first sample and a second sample for a cube map. A cube map path is computed between the first sample and the second sample. A distance is computed between the first sample and the second sample, wherein the distance is measured using the cube map path. LOD filtering is then implemented by using the distance between the first sample and the second sample.
摘要:
Systems and methods used for font filtering may also be used to perform texture blits. Texture data is read in blocks that are coarsely aligned. Font engines may be used to align the texture data as specified by a copy (blit) instruction to provide a finely aligned region of the texture data within a font filter footprint. The finely aligned region is then bilinearly filtered using a “nearest” mode to provide the bit aligned region of the texture map specified by the copy instruction.
摘要:
Vertex data can be accessed for a graphics primitive. The vertex data includes homogeneous coordinates for each vertex of the primitive. The homogeneous coordinates can be used to determine perspective-correct barycentric coordinates that are normalized by the area of the primitive. The normalized perspective-correct barycentric coordinates can be used to determine an interpolated value of an attribute for the pixel. These operations can be performed using adders and multipliers implemented in hardware.
摘要:
Systems and methods for modifying the number of texture samples used to produce an anisotropically filtered texture mapped pixel may improve texture mapping performance. When the number of texture samples is reduced, fewer texels are read and fewer filtering computations are needed to produce a texture value for an anisotropic footprint. The number of texture samples is reduced based on the mip map level weight. The number of texture samples may also be modified using specific parameters for the coarse and/or fine mip map levels. The spacing between the texture samples along the major axis of anisotropy may be modified to improve image quality or texture cache performance.
摘要:
A pixel center position that is not covered by a primitive covering a portion of the pixel is displaced to lie within a fragment formed by the intersection of the primitive and the pixel. X,y coordinates of a pixel center are adjusted to displace the pixel center position to lie within the fragment, affecting actual texture map coordinates or barycentric weights. Alternatively, a centroid sub-pixel sample position is determined based on coverage data for the pixel and a multisample mode. The centroid sub-pixel sample position is used to compute pixel or sub-pixel parameters for the fragment.
摘要:
A system, apparatus, and method are disclosed for modifying positions of sample positions for selectably oversampling pixels to anti-alias non-geometric portions of computer-generated images, such as texture, at least in part, by translating (e.g., shifting) shading sample positions relative to a frame of reference in which there is no relative motion between the geometries and the coverage sample positions. In one embodiment, an exemplary method determines whether a coverage sample position is covered by a geometric primitive. The method includes translating a shading sample position from an original shading sample position to the coverage sample position. This generally occurs if the geometry covers the coverage sample position to form a covered coverage sample position. Further, the method samples a shading value at the covered coverage sample positions for the pixel portion to anti-alias, for example, texture to reduce level of detail (“LOD”) artifacts.
摘要:
Data for data elements (e.g., pixels) can be stored in an addressable storage unit that can store a number of bits that is not a whole number multiple of the number of bits of data per data element. Similarly, a number of the data elements can be transferred per unit of time over a bus, where the width of the bus is not a whole number multiple of the number of bits of data per data element. Data for none of the data elements is stored in more than one of the storage units or transferred in more than one unit of time. Also, data for multiple data elements is packaged contiguously in the storage unit or across the width of the bus.