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公开(公告)号：US20070143387A1
公开(公告)日：2007-06-21
申请号：US11311971
申请日：2005-12-19
IPC分类号： G06F17/14
CPC分类号： G06J1/00
摘要： A first device is described. The first device may include a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit may have an input to receive a vector having N digital values and an output to output N first output signals, a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H, and a conversion (DAC) circuit coupled to the sign-adjustment circuit. Outputs from the DAC circuit may be summed to produce an output.
摘要翻译： 描述第一设备。 第一装置可以包括线性变换电路以实现矩阵D的乘法。线性变换电路可以具有用于接收具有N个数字值的矢量的输入和用于输出N个第一输出信号的输出，用于调整的符号调整电路 根据一组系数H包括至少N个N个第一输出信号的子集的符号，以及耦合到符号调整电路的转换（DAC）电路。 来自DAC电路的输出可以相加以产生输出。
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公开(公告)号：US20110184999A1
公开(公告)日：2011-07-28
申请号：US13083473
申请日：2011-04-08
IPC分类号： G06F17/14
CPC分类号： G06J1/00
摘要： A first device includes a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit as an input to receive a vector having N digital values and an output to output N first output signals. The linear transformation circuit optionally includes a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H. The linear transformation circuit includes a digital-to-analog conversion (DAC) circuit coupled to the output of the sign-adjustment circuit. Outputs from the DAC circuit are summed to produce an output.
摘要翻译： 第一装置包括用矩阵D进行乘法的线性变换电路。线性变换电路作为用于接收具有N个数字值的矢量和输出以输出N个第一输出信号的输入。 线性变换电路可选地包括符号调整电路，用于根据一组系数H来调整包括至少M个N个第一输出信号的子集的符号。线性变换电路包括数模转换（DAC） ）电路耦合到符号调节电路的输出。 来自DAC电路的输出相加以产生输出。
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公开(公告)号：US07925686B2
公开(公告)日：2011-04-12
申请号：US11311971
申请日：2005-12-19
CPC分类号： G06J1/00
摘要： A first device is described. The first device may include a linear transformation circuit to implement multiplication by a matrix D. The linear transformation circuit may have an input to receive a vector having N digital values and an output to output N first output signals, a sign-adjustment circuit to adjust signs of a subset including at least M of the N first output signals in accordance with a set of coefficients H, and a conversion (DAC) circuit coupled to the sign-adjustment circuit. Outputs from the DAC circuit may be summed to produce an output.
摘要翻译： 描述第一设备。 第一装置可以包括线性变换电路以实现矩阵D的乘法。线性变换电路可以具有用于接收具有N个数字值的矢量的输入和用于输出N个第一输出信号的输出，用于调整的符号调整电路 根据一组系数H包括至少N个N个第一输出信号的子集的符号，以及耦合到符号调整电路的转换（DAC）电路。 来自DAC电路的输出可以相加以产生输出。
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公开(公告)号：US20070058744A1
公开(公告)日：2007-03-15
申请号：US11557101
申请日：2006-11-06
申请人： Amir Amirkhany , Vladimir Stojanovic , Elad Alon , Jared Zerbe , Mark Horowitz
发明人： Amir Amirkhany , Vladimir Stojanovic , Elad Alon , Jared Zerbe , Mark Horowitz
CPC分类号： G06F17/141 , G06J1/005
摘要： A transform circuit includes a first circuit and a second circuit. The first circuit and the second circuit implement first and second mappings that together generate a pre-defined transform of N digital data symbols. The first circuit maps a set of N digital data symbols from N parallel data streams to N analog data symbols by generating N sets of first weighted sums of the N digital data symbols. Each respective first weighted sum is defined by a respective set of pre-determined first weighting values in a first matrix. The second circuit maps the N analog data symbols to a sequence of N output signals over N time intervals. Each of the N output signals corresponds to a respective second weighted sum of the N analog data symbols. Each respective second weighted sum is defined by a respective set of pre-determined second weighting values in a second matrix.
摘要翻译： 变换电路包括第一电路和第二电路。 第一电路和第二电路实现一起产生N个数字数据符号的预定义变换的第一和第二映射。 第一电路通过产生N个数字数据符号的第一加权和的N组，将来自N个并行数据流的一组N个数字数据符号映射到N个模拟数据符号。 每个相应的第一加权和由第一矩阵中的预定的第一加权值的相应集合来定义。 第二电路在N个时间间隔内将N个模拟数据符号映射到N个输出信号的序列。 N个输出信号中的每一个对应于N个模拟数据符号的相应的第二加权和。 每个相应的第二加权和由第二矩阵中的预定的第二加权值的相应集合来定义。
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公开(公告)号：US09165615B2
公开(公告)日：2015-10-20
申请号：US13636515
申请日：2011-03-14
CPC分类号： G11C7/1006 , G11C7/02
摘要： Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links.
摘要翻译： 编码器和解码器电路，用于对一系列代码字进行编码和解码一系列数据字。 数据字包括L个符号。 代码字包括M个符号，其中M大于L.一组紧密耦合的M个链路，用于在每一个码字序列中传送相应的符号。 选择码字使得在一系列码字中的每两个连续码字之间，在M链路的子集上出现从低到高和高到低的相等数量的转换。
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公开(公告)号：US08917783B2
公开(公告)日：2014-12-23
申请号：US13129998
申请日：2009-12-03
CPC分类号： H04L25/0272 , H04L25/03878
摘要： The frequency response of a first component signal path of a differential signaling link is adjusted to off-set a notch in the frequency response from a corresponding notch in the frequency response of a second component signal path of the differential signaling link.
摘要翻译： 差分信号链路的第一分量信号路径的频率响应被调整为在差分信令链路的第二分量信号路径的频率响应中的相应陷波的频率响应中偏移一个陷波。
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公开(公告)号：US09071481B2
公开(公告)日：2015-06-30
申请号：US14342367
申请日：2012-08-10
CPC分类号： H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
摘要： A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.
摘要翻译： 校准反馈均衡器以补偿接收信号中的估计符号间干扰和采样设备的偏移。 判定反馈均衡器被配置为使得采样电路的输出信号表示在校准下的输入信号和采样电路的基准之间的比较。 在包括预定图案的通信信道上接收输入信号。 将预定模式与输出信号进行比较，以确定用于配置考虑到偏移和符号间干扰效应两者的采样电路的调整参考。
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8.发明申请Methods and Circuits for Controlling Amplifier Gain Over Process, Voltage, and Temperature 审中-公开控制放大器过程，电压和温度增益的方法和电路公开(公告)号：US20120139638A1
公开(公告)日：2012-06-07
申请号：US13310609
申请日：2011-12-02
申请人： Kambiz Kaviani , Amir Amirkhany , Aliazam Abbasfar
发明人： Kambiz Kaviani , Amir Amirkhany , Aliazam Abbasfar
IPC分类号： H03F3/04
CPC分类号： H03F3/45183 , H03F3/45197 , H03F3/45632 , H03F2200/447 , H03F2203/45008 , H03F2203/45048 , H03F2203/45078 , H03F2203/45306 , H03F2203/45488 , H03F2203/45686 , H03G1/0029 , H03G1/007
摘要： A receiver includes an amplifier and a transconductance bias circuit. The amplifier gain is largely determined by transconductance and load impedance. The transconductance bias circuit varies the transconductance in inverse proportion to the load impedance to maintain the gain over process, voltage, and temperature. Differential amplifiers can use separate transconductance bias circuits for each amplifier leg, and the bias circuits can be independently controlled to minimize common-mode gain and voltage offsets.
摘要翻译： 接收器包括放大器和跨导偏置电路。 放大器增益主要取决于跨导和负载阻抗。 跨导偏置电路会将跨导与负载阻抗成反比变化，以保持增益超过过程，电压和温度。 差分放大器可以为每个放大器支路使用单独的跨导偏置电路，并且可以独立控制偏置电路以最小化共模增益和电压偏移。
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公开(公告)号：US20100128813A1
公开(公告)日：2010-05-27
申请号：US12515390
申请日：2007-11-09
申请人： Aliazam Abbasfar , Amir Amirkhany
发明人： Aliazam Abbasfar , Amir Amirkhany
CPC分类号： H04L25/03343 , H04L5/0007 , H04L5/06 , H04L25/03057 , H04L27/2637 , H04L27/2644 , H04L2025/03414 , H04L2025/03426 , H04L2025/0349
摘要： A data transmission circuit comprises a plurality of data preparation circuits and a combiner. Each data preparation circuit receives a respective data stream and generates a respective sub-channel signal. Each respective data stream has a respective symbol rate and a respective Nyquist bandwidth. The combiner combines the respective sub-channel signals to generate a data transmission signal having an associated bandwidth. The bandwidth associated with the data transmission signal is greater than or equal to the sum of the Nyquist bandwidths for the respective data streams. Each data preparation circuit comprises a programmable linear equalizer that equalizes the respective sub-channel signal across the bandwidth of the data transmission signal.
摘要翻译： 数据传输电路包括多个数据准备电路和组合器。 每个数据准备电路接收相应的数据流并产生相应的子信道信号。 每个相应的数据流具有相应的符号率和相应的奈奎斯特带宽。 组合器组合各个子信道信号以产生具有相关带宽的数据传输信号。 与数据传输信号相关联的带宽大于或等于相应数据流的奈奎斯特带宽的总和。 每个数据准备电路包括一个可编程线性均衡器，用于跨数据传输信号的带宽均衡相应的子信道信号。
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公开(公告)号：US20140226707A1
公开(公告)日：2014-08-14
申请号：US14342367
申请日：2012-08-10
CPC分类号： H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
摘要： A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.
摘要翻译： 校准反馈均衡器以补偿接收信号中的估计符号间干扰和采样设备的偏移。 判定反馈均衡器被配置为使得采样电路的输出信号表示在校准下的输入信号和采样电路的基准之间的比较。 在包括预定图案的通信信道上接收输入信号。 将预定模式与输出信号进行比较，以确定用于配置考虑到偏移和符号间干扰效应两者的采样电路的调整参考。
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