公开(公告)号：US4739471A

公开(公告)日：1988-04-19

申请号：US750701

申请日：1985-06-28

申请人： Allen J. Baum ,  William R. Bryg

发明人： Allen J. Baum ,  William R. Bryg

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/35 ,  G06F9/45 ,  G06F12/02 ,  G06F12/08 ,  G06F9/00

CPC分类号： G06F9/30043 ,  G06F8/41 ,  G06F9/35

摘要： A basic instruction for moving a string of bytes in a word has been devised. Because the operations in the instruction are basic, very few variations are necessary to accommodate diversity of lengths and variables. These operations are imbedded in a single code sequence; the compiler can therefore generate exactly the minimum sequence necessary to perform the operations and can precompute many of the operands at compile time, typically completing the instruction within a single cycle time. The control necessary to optimize the operations is then in the compiler instead of the hardware.

摘要翻译： 已经设计了用于移动单词中字节串的基本指令。 由于指令中的操作是基本操作，因此需要极少的变化来适应长度和变量的多样性。 这些操作嵌入在一个代码序列中; 因此，编译器可以精确地生成执行操作所需的最小序列，并且可以在编译时预先计算许多操作数，通常在单个周期内完成指令。 然后在编译器而不是硬件中进行优化操作所需的控制。

公开(公告)号：US4722050A

公开(公告)日：1988-01-26

申请号：US845213

申请日：1986-03-27

申请人： Ruby B. Lee ,  Allen J. Baum ,  Russell Kao

发明人： Ruby B. Lee ,  Allen J. Baum ,  Russell Kao

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/00 ,  G06F9/30

CPC分类号： G06F9/382 ,  G06F12/0859 ,  G06F9/3802 ,  G06F9/3808 ,  G06F9/3822 ,  G06F9/3846

摘要： A computer having a cache memory and a main memory is provided with a transformation unit between the main memory and the cache memory so that at least a portion of an information unit retrieved from the main memory may be transformed during retrieval of the information (fetch) from a main memory and prior to storage in the cache memory (cache). In a specific embodiment, an instruction may be predecoded prior to storage in the cache memory. In another embodiment involving a branch instruction, the address of the target of the branch is calculated prior to storing in the instruction cache. The invention has advantages where a particular instruction is repetitively executed since a needed decode operation which has been partially performed previously need not be repeated with each execution of an instruction. Consequently, the latency time of each machine cycle may be reduced, and the overall efficiency of the computing system can be improved. If the architecture defines delayed branch instructions, such branch instructions may be executed in effectively zero machine cycles. This requires a wider bus and an additional register in the processor to allow the fetching of two instructions from the cache memory in the same cycle.

摘要翻译： 具有高速缓冲存储器和主存储器的计算机在主存储器和高速缓冲存储器之间设置有变换单元，使得从主存储器检索的信息单元的至少一部分可以在检索信息（取出）期间被变换， 从主存储器和存储在缓存内存（cache）之前。 在具体实施例中，可以在存储在高速缓冲存储器中之前对指令进行预解码。 在涉及分支指令的另一实施例中，在存储在指令高速缓存中之前，计算分支目标的地址。 本发明具有重复执行特定指令的优点，因为先前部分执行的所需解码操作不需要在每次执行指令时重复执行。 因此，可以减少每个机器周期的等待时间，并且可以提高计算系统的整体效率。 如果架构定义了延迟分支指令，则可以在有效的零机器周期中执行这种分支指令。 这需要处理器中的更宽的总线和附加寄存器，以允许在同一周期中从高速缓冲存储器中取出两条指令。

公开(公告)号：US4637346A

公开(公告)日：1987-01-20

申请号：US724368

申请日：1985-04-17

申请人： Robert Draper ,  Donald G. Lorentz ,  Allen J. Baum ,  George Economy

发明人： Robert Draper ,  Donald G. Lorentz ,  Allen J. Baum ,  George Economy

IPC分类号： F22B1/16 ,  F22B35/00 ,  F22B1/00

CPC分类号： F22B35/004

摘要： An improved, compact model steam generator having multiple primary systems is described herein. The model steam generator of the invention is capable of simultaneously simulating a plurality of thermo-hydraulic conditions which may exist in various areas of a full-scale nuclear steam generator in order that the effect of these various conditions on the heat exchange tubes within the full-scale generator may be separately monitored. The model steam generator of the invention generally includes a boiler vessel having a primary side which houses a plurality of individually controllable primary systems, a tubesheet, a secondary side, and a plurality of sample heat exchange tubes for transferring heat between each of the individual primary systems and the secondary side of the boiler vessel. A heat flux control system connected to each of the heat sources within the primary systems allows the operator to separately adjust the heat fluxes of each of the ends of the sample tubes disposed within the secondary side of the boiler vessel. In order to reduce the longitudinal and diametrical dimensions of the primary side of the boiler vessel, the heat source used in each of the individual primary systems is preferably a single, high-intensity electrical heater formed from a coil or other high density configuration of electrical resistance wire. Moreover, each of these primary systems may be housed within the tube-receiving bores of the tube sheet of the boiler vessel in order to minimize the longitudinal dimensions of the primary side even further.

摘要翻译： 本文描述了具有多个主要系统的改进的紧凑型蒸汽发生器。 本发明的模型蒸汽发生器能够同时模拟可能存在于全尺寸核蒸汽发生器的各个区域中的多个热液压条件，以便这些各种条件对热交换管的影响在整个 尺寸发生器可以单独监控。 本发明的模型蒸汽发生器通常包括具有初级侧的锅炉容器，其容纳多个单独可控的主系统，管板，次级侧和多个样品热交换管，用于在每个单独的主要系统之间传递热量 系统和锅炉容器的二次侧。 连接到主系统内的每个热源的热通量控制系统允许操作者分别调节设置在锅炉容器的次级侧内的样品管的每个端部的热通量。 为了减小锅炉容器的初级侧的纵向尺寸和直径尺寸，每个单个主系统中使用的热源优选是由线圈或其它高密度配置的电气形成的单个高强度电加热器 电阻丝。 此外，这些主要系统中的每一个可以容纳在锅炉容器的管板的管接收孔内，以便进一步最小化初级侧的纵向尺寸。

公开(公告)号：US07957428B2

公开(公告)日：2011-06-07

申请号：US10850809

申请日：2004-05-21

申请人： Maurice B. Steinman ,  Rahul R. Shah ,  Naveen Cherukuri ,  Aaron T. Spink ,  Allen J. Baum ,  Sanjay Dabral ,  Tim Frodsham ,  David S. Dunning ,  Theodore Z. Schoenborn

发明人： Maurice B. Steinman ,  Rahul R. Shah ,  Naveen Cherukuri ,  Aaron T. Spink ,  Allen J. Baum ,  Sanjay Dabral ,  Tim Frodsham ,  David S. Dunning ,  Theodore Z. Schoenborn

IPC分类号： H04J3/04

CPC分类号： G06F13/4018 ,  G06F13/4009 ,  Y02D10/14 ,  Y02D10/151

摘要： Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

摘要翻译： 本发明的实施例提供了一种用于将链路划分成一个或多个缩小宽度链路的算法。 对于本发明的一个实施例，采用复用方案来实现特定循环冗余校验所需的位传输顺序。 多路复用的输出位随后在芯片上转动，以减少车载路由拥塞。

公开(公告)号：US5303358A

公开(公告)日：1994-04-12

申请号：US4627

申请日：1993-01-14

申请人： Allen J. Baum

发明人： Allen J. Baum

IPC分类号： G06F9/302 ,  G06F9/318 ,  G06F9/30 ,  G06F9/34

CPC分类号： G06F9/3001 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30185

摘要： A method and apparatus for instruction prefixing selectively reconfigures certain of the instructions in the microprocessor's instruction set so as to alter the nature of the operation performed by the instruction and/or the designation of operand or result locations accessed by the operation. A prefix instruction is inserted ahead of a "using" instruction and an operational parameter of the using instruction is modified in accordance with the contents of the prefix instruction. In one application, the prefix instruction may be used to specify a register location for storage of a result of the using instruction's operation or retrieval of an operand. In other applications, the prefix instruction may be used to modify other aspects of instruction execution.

摘要翻译： 用于指令前缀的方法和装置选择性地重新配置微处理器指令集中的某些指令，以便改变由指令执行的操作的性质和/或由操作所访问的操作数或结果位置的指定。 在“使用”指令之前插入前缀指令，并且根据前缀指令的内容修改使用指令的操作参数。 在一个应用中，前缀指令可用于指定用于存储使用指令的操作结果或检索操作数的寄存器位置。 在其他应用中，前缀指令可用于修改指令执行的其他方面。

公开(公告)号：US5001662A

公开(公告)日：1991-03-19

申请号：US345116

申请日：1989-04-28

申请人： Allen J. Baum

发明人： Allen J. Baum

IPC分类号： G06F7/50 ,  G06F7/53 ,  G06F9/302 ,  G06F9/318 ,  G06F9/32 ,  G06F9/34 ,  G06F9/38 ,  G06F15/80

CPC分类号： G06F9/30014 ,  G06F15/8015 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30192

摘要： Methods and apparatus are provided for performing multi-gauge arithmetic operations in a microprocessor CPU. Special purpose instructions facilitate parallel processing of individual bytes or half words of data words without requiring that the processor's mode be separately controlled. A byte/half word mode flag is provided to control the "width" of narrow gauge operation. Add partial, substract partial and compare partial instructions operate on corresponding bytes or half words of two operands and return independent byte or half word results. Multiply partial instructions multiply byte or half word multiplicands by a common multiplier and return independent byte or half word products. The multi-gauge arithmetic operations of the present invention have particular application to graphics processing where repetitive operations are performed on large arrays of pixel data.

公开(公告)号：US20130007046A1

公开(公告)日：2013-01-03

申请号：US13175772

申请日：2011-07-01

申请人： Allen J. Baum ,  Sailesh Kottapalli ,  Vedaraman Geetha

发明人： Allen J. Baum ,  Sailesh Kottapalli ,  Vedaraman Geetha

IPC分类号： G06F17/30

CPC分类号： G06F13/4022

摘要： Methods and apparatus relating to dynamically routing data responses directly to a requesting processor core are described. In one embodiment, data returned in response to a data request is to be directly transmitted to a requesting agent based on information stored in a route back table. Other embodiments are also disclosed.

摘要翻译： 描述了将数据响应直接动态地路由到请求处理器核心的方法和装置。 在一个实施例中，响应于数据请求返回的数据将基于存储在路由表中的信息直接发送到请求代理。 还公开了其他实施例。

公开(公告)号：US07607071B2

公开(公告)日：2009-10-20

申请号：US11046491

申请日：2005-01-28

申请人： Henk Gomarus Caroline Neefs ,  Allen J. Baum

发明人： Henk Gomarus Caroline Neefs ,  Allen J. Baum

IPC分类号： H03M13/00

CPC分类号： H03M13/3746 ,  H03M13/09 ,  H03M13/098

摘要： An embodiment of the present invention is a technique to perform error correction using a trial-and-error method. A syndrome generator provides a generation of a data syndrome of a data word modified according to a selection of at least one of error correcting parameters. The data word is associated with at least one transaction performed on a unit. A controller controls iterating the generation of the data syndrome.

摘要翻译： 本发明的实施例是使用试错法进行纠错的技术。 校正子发生器提供根据至少一个纠错参数的选择修改的数据字的数据校正子的产生。 数据字与在一个单元上执行的至少一个事务相关联。 控制器控制迭代数据综合征的产生。

公开(公告)号：US07024533B2

公开(公告)日：2006-04-04

申请号：US10441451

申请日：2003-05-20

申请人： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

发明人： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

IPC分类号： G06F12/00

CPC分类号： G06F13/1689

摘要： A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

公开(公告)号：US06636955B1

公开(公告)日：2003-10-21

申请号：US09652480

申请日：2000-08-31

申请人： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

发明人： Richard E. Kessler ,  Peter J. Bannon ,  Maurice B. Steinman ,  Scott E. Breach ,  Allen J. Baum ,  Gregg A. Bouchard

IPC分类号： G06F1200

CPC分类号： G06F13/1689

摘要： A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself. Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

摘要翻译： 计算机系统具有存储器控制器，其包括耦合到多个存储器通道的读取缓冲器。 存储器控制器有利地消除由存储器模块位于与存储器控制器不同的距离处引起的通道间偏移。 存储器控制器优选地包括用于每个存储器通道的通道接口和同步逻辑电路。 该电路包括读取和写入缓冲区，读取缓冲区的加载和卸载指针。 卸载指针逻辑生成卸载指针，加载指针逻辑生成加载指针。 指针优选地是根据两个不同的时钟信号递增的自由运行指针。 负载指针根据由存储器控制器产生的时钟增加，但是已经被引出到存储器模块和从存储器模块返回。 卸载指针根据计算机系统本身产生的时钟增加。 因为每个存储器通道的迹线长度可能不同，所以存储器模块将读数据提供给存储器控制器所花费的时间可能对于每个通道而言可能不同。 “偏斜”被定义为数据到达最早通道时和数据到达最新通道之间的时间差。 在系统初始化期间，指针是同步的。 初始化之后，这些指针用于加载和卸载读取缓冲区，从而消除内部信道偏移的影响。