公开(公告)号：US20170155529A1

公开(公告)日：2017-06-01

申请号：US15376188

申请日：2016-12-12

申请人： Altera Corporation

发明人： Edward Aung ,  Henry Lui ,  Paul Butler ,  John Turner ,  Rakesh Patel ,  Chong Lee

IPC分类号： H04L25/03 ,  H04L7/033 ,  H04L25/02

CPC分类号： H04L25/03273 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/02 ,  H04L7/033 ,  H04L7/0337 ,  H04L25/0228

摘要： A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.