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1.发明授权Method of generating a ring signal in a subscriber line interface circuit technical field 有权在用户线接口电路技术领域生成振铃信号的方法公开(公告)号：US06973181B2
公开(公告)日：2005-12-06
申请号：US10323542
申请日：2002-12-18
申请人： Anders Emericks , Henrik Hellberg
发明人： Anders Emericks , Henrik Hellberg
摘要： In a method and a device for controlling the magnitude of the generated ring signal in a the Subscriber Line Interface Circuit (SLIC) the voltage of the A and B lines to the subscriber from the SLIC is compared to a reference voltage. The device is arranged to control the magnitude of the generated ring signal voltage in response to the outcome of the comparison. In particular, the device is arranged to control the ring signal voltage so that the ring signal voltage is reduced if the voltage on the A or B line exceeds the reference voltage. Also, the reference voltage is preferably chosen so that there is no risk for saturation of the final stages. The reference voltage is preferably selected to have a value being related to the value of the negative supply voltage.
摘要翻译： 在用户线路接口电路（SLIC）中用于控制所生成的振铃信号的大小的方法和装置中，将来自SLIC的用户的A和B线的电压与参考电压进行比较。 该装置被布置成响应于比较的结果来控制所产生的环形信号电压的幅度。 特别地，该装置被布置成控制环形信号电压，使得如果A或B线上的电压超过参考电压，则环形信号电压降低。 此外，优选地选择参考电压，使得不存在最终级的饱和的风险。 参考电压优选地选择为具有与负电源电压的值相关的值。
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公开(公告)号：US06498849B1
公开(公告)日：2002-12-24
申请号：US09678676
申请日：2000-10-04
申请人： Henrik Hellberg , Anders Emericks
发明人： Henrik Hellberg , Anders Emericks
IPC分类号： H04M100
CPC分类号： H04M19/005
摘要： To reduce power losses in a SLIC comprising first and second current amplifiers supplying line current to respective wires of a two-wire transmission line to a load, a line current detector detects line currents below a threshold value. For line currents above the threshold value, the second amplifier is supplied from a first battery with a substantially constant voltage. A voltage regulator is connected with its output terminal to the second amplifier, with its current supply terminal to a second battery of higher absolute voltage than said first battery, and with its input terminal to the detector. In response to line currents below said threshold value, the detector outputs control signals proportional to the detected line currents to control the output terminal of the voltage regulator to supply the second amplifier as well as the load from the second battery.
摘要翻译： 为了降低SLIC中的功率损耗，该SLIC包括将线电流提供给负载的双线传输线的相应线的第一和第二电流放大器，线路电流检测器检测低于阈值的线路电流。 对于高于阈值的线路电流，第二放大器由具有基本恒定电压的第一电池供电。 电压调节器与其输出端子连接到第二放大器，其电流源端子具有比所述第一电池更高的绝对电压的第二电池，并且其输入端子连接到检测器。 响应于低于所述阈值的线路电流，检测器输出与检测到的线路电流成比例的控制信号，以控制电压调节器的输出端子以提供第二放大器以及来自第二电池的负载。
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3.发明授权Subscriber line interface circuit which automatically adjusts the signal headroom on a telephone line and a method of doing the same 失效用户线路接口电路，其自动调节电话线路上的信号余量，并进行相同的方法
公开(公告)号：US06119090A
公开(公告)日：2000-09-12
申请号：US89499
申请日：1998-06-03
CPC分类号： H04M19/005
摘要： In a subscriber line interface circuit connected to a two-wire telephone line (A and B lines) for transmitting AC signals, one of the wires (e.g., the A line) is set to a DC voltage lower (i.e., more negative) than a first DC voltage (GND), while the second wire (e.g., the B wire) is set to a DC voltage lower than the DC voltage of the first wire, but higher than a second DC voltage (VREG). A first voltage generator is provided for setting a first threshold voltage (VTHA) between the first DC voltage (GND) and the DC voltage of the first wire. A second voltage generator is provided for setting a second threshold voltage (VTHB) between the second DC voltage (VREG) and the D voltage for the second wire. The first and second threshold voltages are utilized for transmission and reception of AC signals on the respective A and B wires. As long as the instantaneous value (VA) of the signal on the first wire (A) equals the first threshold voltage (VTHA) and/or the instantaneous value (VB) of the signal on the second wire (B) equals the second threshold voltage (VTHB), the subscriber line interface circuit automatically adjusts the signal headroom to the actual amplitude of the AC signals by controlling the voltage difference (VA) between the first DC voltage (GND) and the DC voltage of the first wire (A) and/or the voltage difference (VB) between the DC voltage of the second wire (B) and the second DC voltage (VREG).
摘要翻译： 在连接到用于发送AC信号的双线电话线（A和B线）的用户线接口电路中，其中一条线（例如，A线）被设置为比直流电压低（即更负） 第一直流电压（GND），而第二线（例如，B线）被设置为低于第一线的直流电压但高于第二直流电压（VREG）的直流电压。 提供第一电压发生器，用于设置第一直流电压（GND）和第一导线的直流电压之间的第一阈值电压（VTHA）。 提供第二电压发生器，用于设置第二线路的第二直流电压（VREG）和D电压之间的第二阈值电压（VTHB）。 第一和第二阈值电压用于在相应的A和B电线上发送和接收AC信号。 只要第一线（A）上的信号的瞬时值（VA）等于第二线（B）上的信号的第一阈值电压（VTHA）和/或瞬时值（VB）等于第二阈值 电压（VTHB），用户线路接口电路通过控制第一直流电压（GND）和第一线（A）的直流电压之间的电压差（VA）自动将信号余量调整到交流信号的实际振幅， 和/或第二导线（B）的直流电压与第二直流电压（VREG）之间的电压差（VB）。
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公开(公告)号：US08437442B2
公开(公告)日：2013-05-07
申请号：US12819910
申请日：2010-06-21
IPC分类号： H03D3/24
CPC分类号： H04L27/0014 , H04L2027/0018
摘要： A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.
摘要翻译： 公开了一种用于产生载波频率信号的方法和装置。 该方法包括产生第一频率信号; 在所述两点调制架构的第一点处注入调制信号; 从所述调制信号产生第二频率信号; 通过混合第一频率信号和第二频率信号来引入第二频率信号以产生混合频率信号并输出从混合频率信号中选择的载波频率信号。
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公开(公告)号：US08368479B2
公开(公告)日：2013-02-05
申请号：US12432777
申请日：2009-04-30
IPC分类号： H03B5/10
CPC分类号： H03L7/0995 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2201/0208 , H03B2201/025 , H03J2200/10
摘要： A VCO device is described that has pre-compensation. Digitally switchable compensation capacitors are selectively activated to adjust operation of the VCO to mitigate undesirable operational effects. In some example embodiments, the digitally switchable compensation capacitors of the VCO are adjusted to compensate for the effects of activating (from a quiescent state) an output buffer driven by the VCO.
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公开(公告)号：US07130416B2
公开(公告)日：2006-10-31
申请号：US09736329
申请日：2000-12-15
申请人： Anders Emericks
发明人： Anders Emericks
CPC分类号： H04M19/001
摘要： A subscriber line interface circuit (1′) for supplying line current (IL′) to a two-wire transmission line connected to a load (RL′), comprises a single current amplifier (3′). That single current amplifier (3′) is to be connected with its output terminal to one (B′) of the wires (A′, B′) of the transmission line, while the other wire (A′) of the transmission line is to be connected to a voltage source (V1′) that can be provided within the subscriber line interface circuit (1′) or external thereto.
摘要翻译： 用于向连接到负载（RL'）的二线传输线提供线路电流（IL'）的用户线路接口电路（1'）包括单个电流放大器（3'）。 该单个电流放大器（3'）将与其输出端子连接到传输线的导线（A'，B'）的一个（B'），而传输线的另一个导线（A'）为 连接到可以在用户线路接口电路（1'）内或其外部提供的电压源（V 1'）。
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公开(公告)号：US06195429B1
公开(公告)日：2001-02-27
申请号：US09053727
申请日：1998-04-02
IPC分类号： H04M124
CPC分类号： G01R19/252 , H04B3/48
摘要： In a subscriber line interface circuit connected to a telephone line having a high potential wire and a low potential wire, an arrangement for generating a signal for determining the line voltage comprises means (7, 10, 11) for alternately charging a capacitor (6), by means of a first DC current, to a first voltage, and discharging the capacitor (6), by means of a second DC current, to a second voltage. Hereby, a sawtooth wave having an amplitude corresponding to the difference between the first and second voltages is produced. This sawtooth wave is converted to a pulse train related to the line voltage, from which the line voltage can be determined.
摘要翻译： 在连接到具有高电位线和低电位线的电话线的用户线接口电路中，用于产生用于确定线路电压的信号的装置包括用于交替地对电容器（6）充电的装置（7,10,11） 通过第一直流电流转换成第一电压，并且通过第二直流电流将电容器（6）放电到第二电压。 因此，产生具有对应于第一和第二电压之间的差的振幅的锯齿波。 该锯齿波被转换为与线路电压相关的脉冲串，从该电压可以确定线路电压。
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8.发明授权公开(公告)号：US08405434B2
公开(公告)日：2013-03-26
申请号：US13213579
申请日：2011-08-19
IPC分类号： H03L7/06
摘要： A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.
摘要翻译： 用于锁相环的数字校准系统包括调谐电压控制器，其被配置为将调谐电压设置为一个值; 相位差量化器，被配置为在将参考信号的相位与反馈信号的相位进行比较之后输出相位差; 数字控制器，被配置为接收PDQ的相位差并控制粗调谐信号，使得PDQ的平均相位差为0; 以及频率校准逻辑，被配置为响应于DC的输出来校准反馈信号。
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公开(公告)号：US08222961B2
公开(公告)日：2012-07-17
申请号：US13016089
申请日：2011-01-28
IPC分类号： H03L7/00
CPC分类号： H03L7/08
摘要： A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) (52) comprising a voltage controlled oscillator (VCO) (53) controlled by means of a tuning voltage (Vtune) is disclosed. An embodiment of the invention compares the VCO tuning voltage (Vtune) to a low threshold voltage (Vlow) and a high threshold voltage (Vhigh), creating an oscillation of the VCO tuning voltage by offsetting the divider value such that the PLL (52) forces the tuning voltage (Vtune) towards the high threshold voltage (Vhigh) when the low threshold voltage (Vlow) is reached, and offsetting the divider value such that said PLL (52) forces the tuning voltage (Vtune) towards the low threshold voltage (Vlow) when the high threshold voltage (Vhigh) is reached, measuring the period of the oscillation between the high and the low threshold voltage of the VCO tuning voltage by counting the number of cycles of a reference clock signal (clk), and comparing the number of reference clock cycles to a reference number of clock cycles to determine the relative loop bandwidth of the PLL (52).
摘要翻译： 公开了一种用于确定包括通过调谐电压（Vtune）控制的压控振荡器（VCO）53的锁相环（PLL）（52））的闭环带宽特性的方法和装置。 本发明的一个实施例将VCO调谐电压（Vtune）与低阈值电压（Vlow）和高阈值电压（Vhigh）进行比较，通过偏移分频器值来产生VCO调谐电压的振荡，使得PLL（52） 当达到低阈值电压（Vlow）时迫使调谐电压（Vtune）朝向高阈值电压（Vhigh），并且偏移分频器值，使得所述PLL（52）迫使调谐电压（Vtune）朝向低阈值电压 （Vhigh）时，通过对参考时钟信号（clk）的周期数进行计数来测量VCO调谐电压的高阈值电压和低阈值电压之间的振荡周期，并比较 参考时钟周期数到参考时钟周期数以确定PLL的相对环路带宽（52）。
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10.发明申请公开(公告)号：US20110298507A1
公开(公告)日：2011-12-08
申请号：US13213579
申请日：2011-08-19
IPC分类号： H03L7/08
摘要： A Digital Calibration System for a Phase Locked Loop includes a Tuning Voltage Controller configured to set the tuning voltage to a value; a Phase Difference Quantizer configured to output a phase difference after comparing a phase of the reference signal with a phase of the feedback signal; a Digital Controller configured to receive the phase difference of the PDQ and control a coarse tuning signal such that an average phase difference of the PDQ is 0; and a Frequency Calibration Logic configured to calibrate the feedback signal in response to the output of the DC.
摘要翻译： 用于锁相环的数字校准系统包括调谐电压控制器，其被配置为将调谐电压设置为一个值; 相位差量化器，被配置为在将参考信号的相位与反馈信号的相位进行比较之后输出相位差; 数字控制器，被配置为接收PDQ的相位差并控制粗调谐信号，使得PDQ的平均相位差为0; 以及频率校准逻辑，被配置为响应于DC的输出来校准反馈信号。
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