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1.发明授权Data communications system with address remapping for expanded external memory access 失效具有地址重映射的数据通信系统，用于扩展的外部存储器访问
公开(公告)号：US5715419A
公开(公告)日：1998-02-03
申请号：US446019
申请日：1989-12-05
CPC分类号： G06F9/342 , G06F12/0623
摘要： A data communications system memory interface circuit (32) is provided which operates within an adapter circuit (10). Adapter circuit (10) comprises a communications processor (28), a system interface (30) and a protocol handler (20) coupled together by an adapter bus (26). Communications processor (28) accesses an external memory (38) through a memory interface (32). Memory interface (32) comprises a map register circuit (36) which comprises a number of map registers (44 through 56). The map registers (44 through 56) each are operable to store a portion of a twenty bit address which may be selected by a multiplexer (42) responsive to control signals generated by a control logic circuit (40). The address portion stored in the map registers (44 through 56) are added to a remaining portion of an address to form a complete twenty bit remapped address. In this manner, communications processor (28), using a sixteen bit internal address bus, can access a twenty bit addressable memory space within external memory (38). System interface (30) comprises an address register circuit (34) which allows for the accessing of arbitrary twenty bit addresses or the accessing of addresses using page address numbers and offset values. The protocol handler (20) comprises a page address register (24) which allows for the accessing of external memory (38) on one kilobyte page boundaries.
摘要翻译： 提供了在适配器电路（10）内操作的数据通信系统存储器接口电路（32）。 适配器电路（10）包括通过适配器总线（26）耦合在一起的通信处理器（28），系统接口（30）和协议处理器（20）。 通信处理器（28）通过存储器接口（32）访问外部存储器（38）。 存储器接口（32）包括地图寄存器电路（36），其包括多个映射寄存器（44至56）。 每个映射寄存器（44至56）可操作以响应于由控制逻辑电路（40）产生的控制信号来存储可由多路复用器（42）选择的二十位地址的一部分。 存储在映射寄存器（44至56）中的地址部分被添加到地址的剩余部分以形成完整的二十位重映射地址。 以这种方式，使用十六位内部地址总线的通信处理器（28）可以访问外部存储器（38）内的二十位可寻址存储器空间。 系统接口（30）包括地址寄存器电路（34），其允许使用页地址号和偏移值访问任意二十位地址或访问地址。 协议处理器（20）包括页面地址寄存器（24），其允许在一个千字节页面边界上访问外部存储器（38）。
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公开(公告)号：US08130889B2
公开(公告)日：2012-03-06
申请号：US11098130
申请日：2005-04-04
IPC分类号： H04L7/02
CPC分类号： H04L7/0338
摘要： A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
摘要翻译： 介绍了一种新颖的接收时序管理器。 本发明的优选实施例包括用于检测数据转换点的边缘检测逻辑，用于在不同采样点存储数据的多个数据触发器，以及多路复用器，用于基于找到的转换点来选择理想采样点。 样品窗口由多个样品制成。 基于数据传输速度和精度要求，样本窗口大小可以设计为比系统时钟周期更小或更大。
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3.发明授权Scheduler, security context cache, packet processor, and authentication, encryption modules 有权调度器，安全上下文缓存，数据包处理器和认证，加密模块公开(公告)号：US09141831B2
公开(公告)日：2015-09-22
申请号：US13165190
申请日：2011-06-21
CPC分类号： H04L63/0485 , G06F7/588 , G06F21/72 , G06F2221/2107 , H04L9/0625 , H04L9/0631 , H04L9/0637 , H04L9/0643 , H04L9/065 , H04L9/0869 , H04L9/3013 , H04L9/32 , H04L9/3236 , H04L9/3239 , H04L9/3242 , H04L47/2441 , H04L63/0428 , H04L63/08 , H04L2209/125 , H04L2209/38 , H04W12/06
摘要： An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
摘要翻译： 电子电路（200）包括一个或多个可编程控制平面引擎（410,460），其可操作以处理分组标题信息并形成至少一个命令，一个或多个可编程数据平面引擎（310,320,370）选择性地可操作 用于响应于所述至少一个命令可选择的多个密码处理中的至少一个;以及耦合到所述数据平面引擎（310）和所述控制平面引擎（410）的可编程主机处理器（100）。 公开了用于其操作和制造的其他处理器，电路，设备和系统和过程。
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公开(公告)号：US20120084575A1
公开(公告)日：2012-04-05
申请号：US13218116
申请日：2011-08-25
IPC分类号： G06F1/26
CPC分类号： G06F13/14 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A method is provided for scaling voltage in an integrated circuit. A calibration operation is performed on a functional module on the integrated circuit periodically at a rate T1. At least one parameter on the integrated circuit in monitored to determine when a performance threshold is reached. A change is initiated to an operating voltage for a portion of the integrated circuit in response to reaching the threshold. The rate of performing calibration operation is increased to a higher rate T2 for a window of time W in response to initiating the change in operating voltage, after which the rate of performing calibration is returned to the rate T1.
摘要翻译： 提供了一种用于缩放集成电路中的电压的方法。 在速率T1周期性地对集成电路上的功能模块执行校准操作。 监控的集成电路上至少有一个参数用于确定何时达到性能阈值。 响应于达到阈值，针对集成电路的一部分的工作电压发生变化。 响应于启动操作电压的变化，执行校准操作的速率增加到用于时间窗口W的较高速率T2，之后执行校准的速率返回到速率T1。
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5.发明申请Security Processing Engines, Circuits and Systems and Adaptive Processes and Other Processes 有权安全处理引擎，电路和系统以及自适应过程和其他过程公开(公告)号：US20120011351A1
公开(公告)日：2012-01-12
申请号：US13165190
申请日：2011-06-21
CPC分类号： H04L63/0485 , G06F7/588 , G06F21/72 , G06F2221/2107 , H04L9/0625 , H04L9/0631 , H04L9/0637 , H04L9/0643 , H04L9/065 , H04L9/0869 , H04L9/3013 , H04L9/32 , H04L9/3236 , H04L9/3239 , H04L9/3242 , H04L47/2441 , H04L63/0428 , H04L63/08 , H04L2209/125 , H04L2209/38 , H04W12/06
摘要： An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
摘要翻译： 电子电路（200）包括一个或多个可编程控制平面引擎（410,460），其可操作以处理分组标题信息并形成至少一个命令，一个或多个可编程数据平面引擎（310,320,370）选择性地可操作 用于响应于所述至少一个命令可选择的多个密码处理中的至少一个;以及耦合到所述数据平面引擎（310）和所述控制平面引擎（410）的可编程主机处理器（100）。 公开了用于其操作和制造的其他处理器，电路，设备和系统和过程。
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公开(公告)号：US09098438B2
公开(公告)日：2015-08-04
申请号：US13218116
申请日：2011-08-25
CPC分类号： G06F13/14 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A method is provided for scaling voltage in an integrated circuit. A calibration operation is performed on a functional module on the integrated circuit periodically at a rate T1. At least one parameter on the integrated circuit in monitored to determine when a performance threshold is reached. A change is initiated to an operating voltage for a portion of the integrated circuit in response to reaching the threshold. The rate of performing calibration operation is increased to a higher rate T2 for a window of time W in response to initiating the change in operating voltage, after which the rate of performing calibration is returned to the rate T1.
摘要翻译： 提供了一种用于缩放集成电路中的电压的方法。 在速率T1周期性地对集成电路上的功能模块执行校准操作。 监控的集成电路上至少有一个参数用于确定何时达到性能阈值。 响应于达到阈值，针对集成电路的一部分的工作电压发生变化。 响应于启动操作电压的变化，执行校准操作的速率增加到用于时间窗口W的较高速率T2，之后执行校准的速率返回到速率T1。
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公开(公告)号：US08983012B2
公开(公告)日：2015-03-17
申请号：US13358183
申请日：2012-01-25
CPC分类号： H04L7/0338
摘要： A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
摘要翻译： 介绍了一种新颖的接收时序管理器。 本发明的优选实施例包括用于检测数据转换点的边缘检测逻辑，用于在不同采样点存储数据的多个数据触发器，以及多路复用器，用于基于找到的转换点来选择理想采样点。 样品窗口由多个样品制成。 基于数据传输速度和精度要求，样本窗口大小可以设计为比系统时钟周期更小或更大。
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公开(公告)号：US20120121051A1
公开(公告)日：2012-05-17
申请号：US13358183
申请日：2012-01-25
CPC分类号： H04L7/0338
摘要： A novel receive timing manager is presented. The preferred embodiment of the present invention comprises an edge detection logic to detect the data transition points, a plurality of data flip-flops for storing data at different sample points, and a multiplexer to select the ideal sample point based on the transition points found. A sample window is made with multiple samples. The sample window size can be designed smaller or greater than the system clock period based on the data transfer speed and accuracy requirement.
摘要翻译： 介绍了一种新颖的接收时序管理器。 本发明的优选实施例包括用于检测数据转换点的边缘检测逻辑，用于在不同采样点存储数据的多个数据触发器，以及多路复用器，用于基于找到的转换点来选择理想采样点。 样品窗口用多个样品制成。 基于数据传输速度和精度要求，样本窗口大小可以设计为比系统时钟周期更小或更大。
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公开(公告)号：US08171186B1
公开(公告)日：2012-05-01
申请号：US13017824
申请日：2011-01-31
CPC分类号： G06F13/4059
摘要： A method for performing write transactions in an interconnect fabric is described. A burst write transaction is received by a bridge coupled to a master. The burst transaction is initiated by a command phase that includes a wait state attribute. The bridge is also coupled to a second bus that is coupled to a slave destination device or to another bridge. The bridge may initiate a cut-through transaction to the second bus when the wait state attribute indicates a master inserted wait state will not be incurred during the burst transaction.
摘要翻译： 描述了在互连结构中执行写入事务的方法。 突发写入事务由耦合到主机的桥接收。 突发事务由包括等待状态属性的命令阶段启动。 桥接器还耦合到耦合到从属目的地设备或另一桥接器的第二总线。 当等待状态属性指示在插入事务期间不会发生主插入的等待状态时，桥可以启动到第二总线的直通事务。
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