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    Nonvolatile memory device with simultaneous read/write
    1.
    发明授权
    Nonvolatile memory device with simultaneous read/write 有权
    具有同时读/写功能的非易失性存储器件

    公开(公告)号：US06950337B2

    公开(公告)日：2005-09-27

    申请号：US10719650

    申请日：2003-11-21

    申请人： Andrea Bellini ,  Mauro Sali ,  Alessandro Magnavacca ,  Carlo Lisi

    发明人： Andrea Bellini ,  Mauro Sali ,  Alessandro Magnavacca ,  Carlo Lisi

    IPC分类号： G11C16/26 ,  G11C16/34 ,  G11C16/00

    CPC分类号： G11C16/26 ,  G11C16/344 ,  G11C2216/22

    摘要： A nonvolatile memory device with simultaneous read/write has a memory array formed by a plurality of cells organized into memory banks, and a plurality of first and second sense amplifiers. The device further has a plurality of R/W selectors associated to respective sets of cells and connecting the cells of the respective sets of cells alternately to the first sense amplifiers and to the second sense amplifiers.

    摘要翻译： 具有同时读/写的非易失性存储器件具有由组织到存储体中的多个单元形成的存储器阵列以及多个第一和第二读出放大器。 该装置还具有与相应的单元组相关联的多个R / W选择器，并将各组单元的单元交替地连接到第一读出放大器和第二读出放大器。

    METHOD OF MANAGING A MULTILEVEL MEMORY DEVICE AND RELATED DEVICE
    2.
    发明申请
    METHOD OF MANAGING A MULTILEVEL MEMORY DEVICE AND RELATED DEVICE 有权
    管理多个存储器件的方法及相关器件

    公开(公告)号：US20080266946A1

    公开(公告)日：2008-10-30

    申请号：US12109525

    申请日：2008-04-25

    申请人： Alessandro Magnavacca ,  Francesco Pipitone ,  Carlo Lisi ,  Antonino Geraci

    发明人： Alessandro Magnavacca ,  Francesco Pipitone ,  Carlo Lisi ,  Antonino Geraci

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10

    摘要： A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels.

    摘要翻译： 存储器具有被组织成单词页面的k级单元阵列，每个存储一串位。 存储装置包括输入了N位串的编码电路，并产生相应的k级串。 输入有k级串的程序电路，以存储具有k级的c个单元的组。 读取电路读取存储在具有k个级别的c个单元组中的数据，并生成k级字符串。 输入读取解码电路，其具有从具有k个级别的c个单元的组读取的k级字符串，以生成N位串。 每个页面的字被分组成单词组，每个单词包括具有k个级别的c单元的组，以及存储该单词的至少一个剩余位，以及该页面中的其他单词的相应剩余位， c细胞与k水平。

    Method of managing a multilevel memory device and related device
    3.
    发明授权
    Method of managing a multilevel memory device and related device 有权
    管理多级存储器件及相关器件的方法

    公开(公告)号：US07710772B2

    公开(公告)日：2010-05-04

    申请号：US12109525

    申请日：2008-04-25

    申请人： Alessandro Magnavacca ,  Francesco Pipitone ,  Carlo Lisi ,  Antonio Geraci

    发明人： Alessandro Magnavacca ,  Francesco Pipitone ,  Carlo Lisi ,  Antonio Geraci

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5642 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10

    摘要： A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels.

    摘要翻译： 存储器具有被组织成单词页面的k级单元阵列，每个存储一串位。 存储装置包括输入了N位串的编码电路，并产生相应的k级串。 输入有k级串的程序电路，以存储具有k级的c个单元的组。 读取电路读取存储在具有k个级别的c个单元组中的数据，并生成k级字符串。 输入读取解码电路，其具有从具有k个级别的c个单元的组读取的k级字符串，以生成N位串。 每个页面的字被分组成单词组，每个单词包括具有k个级别的c单元的组，以及存储该单词的至少一个剩余位，以及该页面中的其他单词的相应剩余位， c细胞与k水平。

    Control circuit for an output driving stage of an integrated circuit
    4.
    发明授权
    Control circuit for an output driving stage of an integrated circuit 有权

    公开(公告)号：US06567318B2

    公开(公告)日：2003-05-20

    申请号：US09991493

    申请日：2001-11-21

    申请人： Lorenzo Bedarida ,  Luca Vandi ,  Carlo Lisi ,  Andrea Bellini

    发明人： Lorenzo Bedarida ,  Luca Vandi ,  Carlo Lisi ,  Andrea Bellini

    IPC分类号： G11C1604

    CPC分类号： G05F3/245

    摘要： An impedance control circuit controls the impedance of an integrated output driving stage. The integrated output driving stage includes at least one enabling/disabling transistor and at least one driving transistor. The impedance control circuit includes a variable impedance circuit having an impedance that varies with the temperature in correlation with the impedance of the output driving stage. A control circuit is connected to the variable impedance circuit for generating at least one enabling/disabling signal for the at least one enabling/disabling transistor based upon a control signal correlated to the impedance of the variable impedance circuit. The impedance control circuit also includes a current generating circuit for applying to the variable impedance circuit a current which remains substantially stable as the temperature varies.

    Method and device for timing random reading of a memory device
    6.
    发明授权
    Method and device for timing random reading of a memory device 失效
    用于定时随机读取存储器件的方法和装置

    公开(公告)号：US06956787B2

    公开(公告)日：2005-10-18

    申请号：US10700322

    申请日：2003-11-03

    申请人： Carlo Lisi ,  Marco Ferrario ,  Massimiliano Scotti ,  Emanuele Confalonieri

    发明人： Carlo Lisi ,  Marco Ferrario ,  Massimiliano Scotti ,  Emanuele Confalonieri

    IPC分类号： G11C7/08 ,  G11C7/22 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/04

    摘要： A device for timing random reading of a memory device with a data access time, in which reading is performed by a succession of consecutive operations, the timing device being designed to generate, for each operation, a corresponding timing signal such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration, which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration; the sum of the fixed durations being equal to the data access time of the memory device.

    摘要翻译： 一种用于定时随机读取具有数据访问时间的存储器件的装置，其中通过一系列连续操作执行读取，所述定时装置被设计为针对每个操作产生相应的定时信号，例如导致任何 存储器件的操作条件，相应的操作持续一段等于相应的固定持续时间的时间，其被确定为保证在固定持续时间内完成存储器件的最差工作状态下的操作; 固定持续时间的总和等于存储器件的数据访问时间。

    Method and circuit for programming a memory cell, in particular of the NOR flash type
    7.
    发明授权
    Method and circuit for programming a memory cell, in particular of the NOR flash type 有权
    用于编程存储器单元的方法和电路，特别是NOR闪存型

    公开(公告)号：US07656712B2

    公开(公告)日：2010-02-02

    申请号：US12104118

    申请日：2008-04-16

    申请人： Carlo Lisi ,  Tecla Ghilardi

    发明人： Carlo Lisi ,  Tecla Ghilardi

    IPC分类号： G11C160/06

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

    摘要： A method programs a memory cell comprising: an initial phase in which a continuous voltage is applied to a drain terminal of said memory cell and a suitable programming voltage signal is applied to a gate terminal thereof; a regulation phase in which a constant voltage value is applied to said gate terminal and a voltage value of said drain terminal is regulated so as to be maintained at a fixed value until a threshold voltage value of said memory cell is set at a desired threshold voltage level; and a disable phase that stops said programming and is triggered as soon as a programming current value of said memory cell goes below a reference current value, said reference current value corresponding to the attainment by the threshold voltage value of said memory cell of the desired threshold voltage value. A programming circuit is suitable for implementing this method.

    摘要翻译： 一种对存储单元进行编程的方法，包括：向所述存储单元的漏极端子施加连续电压的初始相位，并将合适的编程电压信号施加到其栅极端; 其中对所述栅极端子施加恒定电压值并且调节所述漏极端子的电压值以将其保持在固定值，直到所述存储单元的阈值电压值被设置为期望的阈值电压 水平; 以及停止所述编程并且一旦所述存储器单元的编程电流值低于参考电流值就被触发的禁止阶段，所述参考电流值对应于所述存储单元的阈值电压值达到期望阈值 电压值。 编程电路适用于实现该方法。

    Circuit for detecting a logic transition with improved stability of the length of a detection signal pulse
    9.
    发明授权
    Circuit for detecting a logic transition with improved stability of the length of a detection signal pulse 有权
    用于检测具有改善的检测信号脉冲长度的稳定性的逻辑转换的电路

    公开(公告)号：US06960951B2

    公开(公告)日：2005-11-01

    申请号：US10698051

    申请日：2003-10-30

    申请人： Emanuele Confalonieri ,  Marco Sforzin ,  Carla Poidomani ,  Carlo Lisi

    发明人： Emanuele Confalonieri ,  Marco Sforzin ,  Carla Poidomani ,  Carlo Lisi

    IPC分类号： G11C8/18 ,  H03K5/08 ,  H03K5/13 ,  H03K5/1534 ,  H03K19/003 ,  H03K3/17

    CPC分类号： H03K5/08 ,  G11C8/18 ,  H03K5/13 ,  H03K5/1534

    摘要： A circuit for detecting a logic transition is proposed. The circuit includes an input terminal for receiving a logic signal, an output terminal for generating a detection signal, two capacitors, in a steady condition a first one of the capacitors and a second one of the capacitors being alternately at a first voltage and at a second voltage, respectively, and exchanging means for bringing the first capacitor to the second voltage and the second capacitor to the first voltage in response to a switching of the logic signal; the circuit further includes means for maintaining a command node at the first voltage in the steady condition, means for generating a reset pulse through the first capacitor in response to the switching, means for bringing the command node to the second voltage in response to the reset pulse, a generator of regulated current for bringing back the command node to the first voltage through the second capacitor, and logic means having a regulated threshold voltage comprised between the first and the second voltage, the logic means asserting the detection signal when the command node is brought to the second voltage and deasserting the detection signal when the command node reaches the threshold voltage.

    摘要翻译： 提出了一种用于检测逻辑转换的电路。 该电路包括用于接收逻辑信号的输入端子，用于产生检测信号的输出端子，稳定状态下的两个电容器，第一电容器中的第一电容器和第二电容器交替地处于第一电压 以及用于响应于所述逻辑信号的切换而使所述第一电容器使所述第二电压和所述第二电容器达到所述第一电压的交换装置; 所述电路还包括用于将所述命令节点维持在所述稳定状态下的所述第一电压的装置，用于响应于所述切换产生通过所述第一电容器的复位脉冲的装置，用于响应于所述复位使所述命令节点进入所述第二电压的装置 脉冲，用于通过第二电容器将指令节点返回到第一电压的调节电流发生器，以及具有包括在第一和第二电压之间的调节阈值电压的逻辑装置，逻辑装置在命令节点 当命令节点达到阈值电压时，被提升到第二个电压并且使该检测信号无效。