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公开(公告)号：US07379005B2
公开(公告)日：2008-05-27
申请号：US11516383
申请日：2006-09-06
申请人： Andreas Wiesbauer , Luis Hernandez , Dietmar Sträussnigg , Daniel Gruber , Richard Gaggl , Martin Clara , Stefan Matschitsch
发明人： Andreas Wiesbauer , Luis Hernandez , Dietmar Sträussnigg , Daniel Gruber , Richard Gaggl , Martin Clara , Stefan Matschitsch
IPC分类号： H03M1/66
摘要： Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter (16) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator (18) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).
摘要翻译： 用于检测参考时钟信号（CLK）中的时钟信号抖动的时钟信号抖动检测电路，具有由参考时钟信号（CLK）计时的开关电容器参考数模转换器（15），并转换数字输入 信号转换为第一电流，电流控制的数模转换器（16），其由参考时钟信号（CLK）计时，并将数字输入信号转换为第二电流，并具有积分器（18） 第一电流和第二电流之间的差异，以产生指示参考时钟信号（CLK）中的时钟信号抖动的信号。
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2.发明授权Circuit configuration for quantization of digital signals and for filtering quantization noise 有权用于数字信号量化和滤波量化噪声的电路配置公开(公告)号：US06570512B1
公开(公告)日：2003-05-27
申请号：US09856382
申请日：2001-08-21
申请人： Jörg Hauptmann , Peter Pessl , Dietmar Sträussnigg
发明人： Jörg Hauptmann , Peter Pessl , Dietmar Sträussnigg
IPC分类号： H03M300
CPC分类号： H03M7/3022
摘要： The invention relates to a circuit configuration for quantization of digital signals and for filtering quantization noise. Said circuit configuration comprises a multitude of digital control loops connected in series and having quantizers. The digital signals having a word length of m-bits are fed to a first control loop in the series. The quantization error signal of each quantizer is filtered and fed back to the corresponding digital control loop. It is then fed to a downstream digital control loop. The quantized output signal of the first digital control loop is adapted to a third word length of u-bits which is smaller than the first word length. Except for the quantized output signal of the first digital control loop, the quantized output signals of the digital control loops of the series are respectively filtered by a digital filter. In an adder, said quantized output signals are then added to the first quantized output signal of the first digital control loop of the series to prevent quantization errors. The output signal of the adder has a second word length of n-bits and represents the quantized output signal of the circuit configuration.
摘要翻译： 本发明涉及数字信号量化和滤波量化噪声的电路结构。 所述电路配置包括串联连接并具有量化器的多个数字控制回路。 具有m位的字长的数字信号被馈送到该系列中的第一控制环路。 对每个量化器的量化误差信号进行滤波并反馈到相应的数字控制回路。 然后将其馈送到下游数字控制回路。 第一数字控制环路的量化输出信号适应于小于第一字长的u位的第三字长。 除了第一数字控制回路的量化输出信号之外，系列的数字控制回路的量化输出信号分别被数字滤波器滤波。 在加法器中，然后将所述量化的输出信号加到串联的第一数字控制环路的第一量化输出信号中，以防止量化误差。 加法器的输出信号具有n位的第二字长，表示电路结构的量化输出信号。
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公开(公告)号：US06968049B2
公开(公告)日：2005-11-22
申请号：US10252738
申请日：2002-09-23
申请人： Gerhard Paoli , Dietmar Sträussnigg
发明人： Gerhard Paoli , Dietmar Sträussnigg
摘要： An apparatus for transmitting charging signals on a data transmission path having a line impedance includes a driver device for setting a line voltage level that corresponds to the line impedance. The driver device is configured to provide, in response to a driver input voltage level, a driver output current and a driver output voltage level. A current detection unit provides a current signal indicative of the driver output current and a current signal matching unit receives the current signal from the current detection unit and adjusts a level of the current signal for further processing by a filter device and by a regulation device. A matching filter unit then matches the driver device to a data transmission path unit.
摘要翻译： 用于在具有线路阻抗的数据传输路径上发送计费信号的装置包括用于设置对应于线路阻抗的线路电压电平的驱动器装置。 驱动器装置被配置为响应于驱动器输入电压电平提供驱动器输出电流和驱动器输出电压电平。 电流检测单元提供指示驱动器输出电流的电流信号，并且电流信号匹配单元从电流检测单元接收电流信号，并调节电流信号的电平，以便由滤波器装置和调节装置进一步处理。 匹配滤波器单元然后将驱动器设备与数据传输路径单元匹配。
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4.发明授权Method and circuit for limiting the power of a signal compiled from spread-coded signals 失效用于限制从扩展编码信号编译的信号的功率的方法和电路公开(公告)号：US07693208B2
公开(公告)日：2010-04-06
申请号：US11175716
申请日：2005-07-06
IPC分类号： H04B1/00
CPC分类号： H04J13/0044 , H04B1/707 , H04B2201/70706 , H04J13/12 , H04J13/20
摘要： The method is used for limiting the power of a transmission-end signal (xn) compiled from a plurality of differently spread-coded signals. In this context, it is assumed that the quantity of spread codes used for the differently spread-coded signals is known as code engagement information (Cch,SF,k; 80). First, correction spread codes are selected by virtue of the engagement information (Cch,SF,k; 80) being evaluated. On the basis of the selected correction codes, a spread-coded correction signal (y′n) is formed which is overlaid with the compiled signal (xn).
摘要翻译： 该方法用于限制从多个不同扩展编码信号编译的发送结束信号（xn）的功率。 在这种情况下，假设用于不同扩展编码信号的扩展码的数量被称为代码参与信息（Cch，SF，k; 80）。 首先，通过正在评估的参与信息（Cch，SF，k; 80）来选择校正扩展码。 基于所选择的校正码，形成与编译信号（xn）重叠的扩展编码校正信号（y'n）。
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公开(公告)号：US07592932B2
公开(公告)日：2009-09-22
申请号：US10971526
申请日：2004-10-22
IPC分类号： H03M7/00
CPC分类号： H03H17/0294 , H03H17/0657 , H03H17/0664 , H04L27/0008
摘要： A method and a device for interpolating or decimating a signal is provided, the signal being processed by a plurality of signal processing means connected in series, which at least comprise means for increasing or reducing a clock rate of the signal and filtering means. To achieve adaptation to different operating modes or transmission standards, individual portions of the signal processing means connected in series can be bridged by bypasses. In addition, filtering parameters of the filtering means can be varied and factors, by which a clock rate of the signal is increased or reduced, can be changed.
摘要翻译： 提供了一种用于内插或抽取信号的方法和装置，该信号由串联连接的多个信号处理装置处理，该信号处理装置至少包括用于增加或减少信号和滤波装置的时钟速率的装置。 为了实现对不同操作模式或传输标准的适应，串联连接的信号处理装置的各个部分可以通过旁路桥接。 此外，可以改变滤波装置的滤波参数，并且可以改变信号的时钟速率增加或减小的因素。
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公开(公告)号：US07027592B1
公开(公告)日：2006-04-11
申请号：US09914417
申请日：2000-03-01
IPC分类号： H04M1/00
CPC分类号： H04B3/23
摘要： A circuit arrangement for two-wire/four-wire conversion in a DMT system, which is connected to a digital reception path, a digital transmission path and also an analog transmission/reception path and which has nonlinear echo cancellation in the time domain of a signal and also linear echo cancellation in the frequency domain of the signal, furthermore comprises a device for adaptation of the nonlinearities in the frequency domain.
摘要翻译： 在DMT系统中用于二线/四线转换的电路装置，其连接到数字接收路径，数字传输路径以及模拟发送/接收路径，并且在时域中具有非线性回波消除 在信号的频域中的信号和线性回波消除，还包括用于在频域中适应非线性的装置。
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7.发明授权Method of compensating for interference in a signal generated by discrete multitone modulation, and circuit configuration for carrying out the method. 有权补偿由离散多音调制产生的信号中的干扰的方法，以及用于执行该方法的电路配置。公开(公告)号：US06647076B1
公开(公告)日：2003-11-11
申请号：US09449717
申请日：1999-11-24
IPC分类号： H03D104
CPC分类号： H04L25/03159 , H04L2025/03414 , H04L2025/03522 , H04L2025/03611
摘要： The invention relates to a method for the compensation of interference in a signal generated by discrete multitone modulation. The signal generated by discrete multitone modulation has a multiplicity of carrier frequencies, and each carrier frequency has a signal vector. An error signal vector is generated from a reference signal vector, which is a signal vector from the multiplicity of signal vectors. The error signal vector is added to each of the remaining signal vectors of the multiplicity of signal vectors for the purpose of compensating for interference. Each of the signal vectors of the multiplicity of signal vectors, except for the reference signal vector, is assigned a set of adjustable coefficients by which the error signal vector is multiplied prior to the addition.
摘要翻译： 本发明涉及一种用于补偿由离散多音调制产生的信号中的干扰的方法。 由离散多音调制产生的信号具有多个载波频率，并且每个载波频率具有信号矢量。 从参考信号向量生成误差信号向量，该参考信号向量是来自多个信号向量的信号向量。 为了补偿干扰，误差信号向量被加到多个信号向量的剩余信号向量的每个中。 除了参考信号向量之外，多个信号矢量的每个信号矢量被分配一组可调整的系数，通过该组可变系数，在加法之前乘以误差信号向量。
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