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    Sensor device for the spectrally resolved capture of valuable documents and a corresponding method
    1.
    发明授权
    Sensor device for the spectrally resolved capture of valuable documents and a corresponding method 有权
    用于光谱解析捕获有价值文件的传感器设备和相应的方法

    公开(公告)号：US08598558B2

    公开(公告)日：2013-12-03

    申请号：US12997152

    申请日：2009-06-04

    申请人： Michael Bloss ,  Martin Clara ,  Wolfgang Deckenbach

    发明人： Michael Bloss ,  Martin Clara ,  Wolfgang Deckenbach

    IPC分类号： G06K9/74

    CPC分类号： G07D7/1205

    摘要： There is described a sensor device for spectrally resolved capture of optical detection radiation which emanates from a value document transported through a capture area of the sensor device in a predefined transport direction, comprising a detection device for spectrally resolved detection of the detection radiation in at least one predefined spectral detection range and emission of detection signals which represent at least one, in particular spectral, property of the detected detection radiation, at least one reference radiation device which emits optical reference radiation which is coupled into a detection beam path of the detection device at least partly in dependence on the position of a value document relative to the capture area, and which has a spectrum with a narrow band which is within the predefined spectral detection range, and/or at least one spectrum with an edge which is within the predefined spectral detection range, and a control and evaluation device which is configured for employing the detection signals which represent the property of the reference radiation, for checking and/or for adjusting the detection device and/or in the evaluation of detection signals which represent the at least one property of detection radiation emanating from the value document.

    摘要翻译： 描述了一种用于光谱分辨的光学检测辐射捕获的传感器装置，该传感器装置从预定传送方向上通过传感器装置的捕获区传送的价值文件产生，包括用于至少在光谱上分辨检测检测辐射的检测装置 一个预定义的光谱检测范围和检测信号的发射，其表示检测到的检测辐射的至少一个，特别是光谱性质的至少一个参考辐射装置，其发射耦合到检测装置的检测光束路径中的光参考辐射 至少部分地取决于价值文档相对于捕获区域的位置，并且具有在预定光谱检测范围内的具有窄带的光谱，和/或至少一个具有位于该捕获区域内的边缘的光谱 预定义的光谱检测范围，以及配置的控制和评估装置 用于采用表示参考辐射的性质的检测信号，用于检查和/或调整检测装置和/或评估表示从价值文件发出的检测辐射的至少一个性质的检测信号。

    SWITCHED CURRENT-CELL WITH INTERMEDIATE STATE
    2.
    发明申请
    SWITCHED CURRENT-CELL WITH INTERMEDIATE STATE 有权
    切换电流与中间状态

    公开(公告)号：US20130222168A1

    公开(公告)日：2013-08-29

    申请号：US13408691

    申请日：2012-02-29

    申请人： Martin CLARA ,  Daniel GRUBER ,  Klatzer WOLFGANG

    发明人： Martin CLARA ,  Daniel GRUBER ,  Klatzer WOLFGANG

    IPC分类号： H03M1/66

    CPC分类号： H03M1/1061 ,  H03M1/742

    摘要： Representative implementations of devices and techniques provide digital-to-analog conversion of signals while minimizing switching related errors. Digital to analog converter (DAC) cells may be arranged to include one or more operating states in addition to binary output states, and may employ a switching technique to “dump” the DAC cell between binary outputs. Further, an array of DAC cells may include a partial set of redundant DAC cells for implementation of the switching technique.

    摘要翻译： 器件和技术的代表性实现提供信号的数模转换，同时最小化与开关相关的错误。 数模转换器（DAC）单元可以被布置为除了二进制输出状态之外还包括一个或多个操作状态，并且可以采用切换技术来在二进制输出之间转储DAC单元。 此外，DAC单元阵列可以包括用于实现切换技术的部分冗余DAC单元组。

    Sigma-Delta Analog-Digital Converter For An Xdsl Multistandard Input Stage
    6.
    发明申请
    Sigma-Delta Analog-Digital Converter For An Xdsl Multistandard Input Stage 失效
    用于Xdsl多标准输入级的Sigma-Delta模拟数字转换器

    公开(公告)号：US20080297385A1

    公开(公告)日：2008-12-04

    申请号：US11661627

    申请日：2004-09-02

    申请人： Martin Clara ,  Antonio Di Giandomenico ,  Joerg Hauptmann ,  Andreas Wiesbauer

    发明人： Martin Clara ,  Antonio Di Giandomenico ,  Joerg Hauptmann ,  Andreas Wiesbauer

    IPC分类号： H03M3/04

    CPC分类号： H03M3/394 ,  H03M3/406 ,  H03M3/424 ,  H03M3/452

    摘要： The invention relates to a sigma-delta analogue/digital converter for an xDSL multi-standard input stage for converting an xDSL signal into a digital output signal, where the sigma-delta analogue/digital converter (1) has: an analogue loop filter (6) which filters an analogue difference signal between the xDSL signal to be converted and a feedback signal in order to produce a filter output signal; a quantizer which quantizes the filter output signal from the analogue loop filter (6) in order to produce the digital output signal; a first digital/analogue converter (16) which converts the digital output signal into the analogue feedback signal; where the analogue loop filter (6) has at least two resonator filter stages (6a, 6b) which respectively comprise a first integrator (6a-1; 6b-1) and a second integrator (6a-2; 6b-2) connected in series therewith, where the second integrator (6a-2; 6b-2) can be connected to the first integrator (6a-1, 6b-1) by means of a controllable feedback switch (6a-3, 6b-3) in order to close a local feedback loop, where the integrator outputs can respectively be connected by means of a controllable switch (25) to a signal input of an adder (27) which adds the output signals from the integrators in order to produce the filter output signal.

    摘要翻译： 本发明涉及一种用于xDSL多标准输入级的Σ-Δ模拟/数字转换器，用于将xDSL信号转换成数字输出信号，其中Σ-Δ模拟/数字转换器（1）具有：模拟环路滤波器 6），其对要转换的xDSL信号和反馈信号之间的模拟差分信号进行滤波，以产生滤波器输出信号; 量化器，其量化来自模拟环路滤波器（6）的滤波器输出信号，以产生数字输出信号; 第一数字/模拟转换器（16），其将数字输出信号转换成模拟反馈信号; 其中模拟环路滤波器（6）具有至少两个分别包括第一积分器（6a-1; 6b-1）和第二积分器（6a-2; 6b-2）的谐振器滤波器级（6a，6b） 其中第二积分器（6a-2; 6b-2）可以通过可控反馈开关（6a-3,6b-3）按顺序连接到第一积分器（6a-1,6b-1） 以闭合局部反馈回路，其中积分器输出可以分别通过可控开关（25）连接到加法器（27）的信号输入端，加法器（27）的信号输入相加来自积分器的输出信号，以产生滤波器输出信号 。

    Compensation circuit for clock jitter compensation
    7.
    发明授权
    Compensation circuit for clock jitter compensation 有权
    时钟抖动补偿补偿电路

    公开(公告)号：US07262723B2

    公开(公告)日：2007-08-28

    申请号：US11451229

    申请日：2006-06-12

    申请人： Dietmar Straussnig ,  Bernd Rainer ,  Andreas Wiesbauer ,  Richard Gaggl ,  Martin Clara ,  Luis Hernandez

    发明人： Dietmar Straussnig ,  Bernd Rainer ,  Andreas Wiesbauer ,  Richard Gaggl ,  Martin Clara ,  Luis Hernandez

    IPC分类号： H03M1/10

    CPC分类号： H03M1/0836 ,  H03M1/66

    摘要： A compensation circuit for a digital/analogue converter, which is clocked by a clock signal comprising a jitter and converts a digital input data signal into an analogue output data signal comprising a jitter error due to said jitter, comprises a measurement circuit for measuring the jitter and a modelling circuit for generating a digital modelled jitter error signal which simulates the jitter error dependent on the measured jitter and the digital input data signal, wherein the digital modelled jitter error signal is subtracted from the digital input data signal.

    摘要翻译： 一种用于数/模转换器的补偿电路，其由包括抖动的时钟信号计时，并将数字输入数据信号转换成包括由于所述抖动引起的抖动误差的模拟输出数据信号，包括用于测量抖动的测量电路 以及用于产生数字建模的抖动误差信号的建模电路，其根据所测量的抖动和数字输入数据信号模拟抖动误差，其中从数字输入数据信号中减去数字建模的抖动误差信号。

    Apparatus and method for spectrally shaping a reference clock signal
    9.
    发明申请
    Apparatus and method for spectrally shaping a reference clock signal 有权
    对参考时钟信号进行频谱整形的装置和方法

    公开(公告)号：US20070057830A1

    公开(公告)日：2007-03-15

    申请号：US11516383

    申请日：2006-09-06

    申请人： Andreas Wiesbauer ,  Luis Hernandez ,  Dietmar Straussnigg ,  Daniel Gruber ,  Richard Gaggl ,  Martin Clara ,  Stefan Matschitsch

    发明人： Andreas Wiesbauer ,  Luis Hernandez ,  Dietmar Straussnigg ,  Daniel Gruber ,  Richard Gaggl ,  Martin Clara ,  Stefan Matschitsch

    IPC分类号： H03L7/00

    CPC分类号： H03L7/08 ,  H03L7/18 ,  H03M3/372 ,  H03M3/464

    摘要： Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter (16) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator (18) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).

    摘要翻译： 用于检测参考时钟信号（CLK）中的时钟信号抖动的时钟信号抖动检测电路，具有由参考时钟信号（CLK）计时的开关电容器参考数模转换器（15），并转换数字输入 信号转换为第一电流，电流控制的数模转换器（16），其由参考时钟信号（CLK）计时，并将数字输入信号转换为第二电流，并具有积分器（18） 第一电流和第二电流之间的差异，以产生指示参考时钟信号（CLK）中的时钟信号抖动的信号。

    Semi-conductor circuit arrangement
    10.
    发明授权
    Semi-conductor circuit arrangement 有权
    半导体电路布置

    公开(公告)号：US06989778B2

    公开(公告)日：2006-01-24

    申请号：US10938741

    申请日：2004-09-10

    申请人： Martin Clara ,  Antonio Di Giandomenico ,  Andreas Wiesbauer

    发明人： Martin Clara ,  Antonio Di Giandomenico ,  Andreas Wiesbauer

    IPC分类号： H03M3/00

    CPC分类号： H03M3/39 ,  H03M3/424 ,  H03M3/452 ,  H03M3/454

    摘要： A semi-conductor circuit arrangement for a continuous time sigma delta modulator for adding analog input signals to a digital fed back signal and for quantizing the totalled signal comprises a voltage to current conversion circuit (10), an adding circuit (20) with a resistor ladder, a quantizing circuit (40) with comparator elements (45) and a digital to analog conversion circuit (30). For each comparator element (45) its respective input signal is formed by a voltage which is released between a tap in front of a corresponding tapping resistor (22) in a first string of the resistor ladder and a tap in front of a corresponding tapping resistor (22) in a second string of the resistor ladder.

    摘要翻译： 一种用于将模拟输入信号加到数字反馈信号并用于量化总计信号的连续时间Σ-Δ调制器的半导体电路装置包括电压 - 电流转换电路（10），具有电阻的加法电路（20） 梯形图，具有比较器元件（45）和数模转换电路（30）的量化电路（40）。 对于每个比较器元件（45），其相应的输入信号由在电阻梯的第一串中的对应的分接电阻器（22）前面的抽头和相应的分接电阻器前面的抽头之间的抽头释放的电压形成 （22）在电阻梯的第二串中。