公开(公告)号：US07379005B2

公开(公告)日：2008-05-27

申请号：US11516383

申请日：2006-09-06

申请人： Andreas Wiesbauer ,  Luis Hernandez ,  Dietmar Sträussnigg ,  Daniel Gruber ,  Richard Gaggl ,  Martin Clara ,  Stefan Matschitsch

发明人： Andreas Wiesbauer ,  Luis Hernandez ,  Dietmar Sträussnigg ,  Daniel Gruber ,  Richard Gaggl ,  Martin Clara ,  Stefan Matschitsch

IPC分类号： H03M1/66

CPC分类号： H03L7/08 ,  H03L7/18 ,  H03M3/372 ,  H03M3/464

摘要： Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter (16) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator (18) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).

摘要翻译： 用于检测参考时钟信号（CLK）中的时钟信号抖动的时钟信号抖动检测电路，具有由参考时钟信号（CLK）计时的开关电容器参考数模转换器（15），并转换数字输入 信号转换为第一电流，电流控制的数模转换器（16），其由参考时钟信号（CLK）计时，并将数字输入信号转换为第二电流，并具有积分器（18） 第一电流和第二电流之间的差异，以产生指示参考时钟信号（CLK）中的时钟信号抖动的信号。

公开(公告)号：US20070057830A1

公开(公告)日：2007-03-15

申请号：US11516383

申请日：2006-09-06

申请人： Andreas Wiesbauer ,  Luis Hernandez ,  Dietmar Straussnigg ,  Daniel Gruber ,  Richard Gaggl ,  Martin Clara ,  Stefan Matschitsch

发明人： Andreas Wiesbauer ,  Luis Hernandez ,  Dietmar Straussnigg ,  Daniel Gruber ,  Richard Gaggl ,  Martin Clara ,  Stefan Matschitsch

IPC分类号： H03L7/00

CPC分类号： H03L7/08 ,  H03L7/18 ,  H03M3/372 ,  H03M3/464

摘要： Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter (16) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator (18) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).

摘要翻译： 用于检测参考时钟信号（CLK）中的时钟信号抖动的时钟信号抖动检测电路，具有由参考时钟信号（CLK）计时的开关电容器参考数模转换器（15），并转换数字输入 信号转换为第一电流，电流控制的数模转换器（16），其由参考时钟信号（CLK）计时，并将数字输入信号转换为第二电流，并具有积分器（18） 第一电流和第二电流之间的差异，以产生指示参考时钟信号（CLK）中的时钟信号抖动的信号。

公开(公告)号：US20110089994A1

公开(公告)日：2011-04-21

申请号：US12580588

申请日：2009-10-16

申请人： Martin Clara ,  Daniel Gruber ,  Wolfgang Klatzer

发明人： Martin Clara ,  Daniel Gruber ,  Wolfgang Klatzer

IPC分类号： H03K3/01

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： The present disclosure relates to threshold voltage modification via a voltage generator connected to bulk nodes of transistors.

摘要翻译： 本公开涉及经由连接到晶体管的体节点的电压发生器的阈值电压修改。

公开(公告)号：US08547268B2

公开(公告)日：2013-10-01

申请号：US13408691

申请日：2012-02-29

申请人： Martin Clara ,  Daniel Gruber ,  Klatzer Wolfgang

发明人： Martin Clara ,  Daniel Gruber ,  Klatzer Wolfgang

IPC分类号： H03M1/66

CPC分类号： H03M1/1061 ,  H03M1/742

摘要： Representative implementations of devices and techniques provide digital-to-analog conversion of signals while minimizing switching related errors. Digital to analog converter (DAC) cells may be arranged to include one or more operating states in addition to binary output states, and may employ a switching technique to “dump” the DAC cell between binary outputs. Further, an array of DAC cells may include a partial set of redundant DAC cells for implementation of the switching technique.

摘要翻译： 器件和技术的代表性实现提供信号的数模转换，同时最小化与开关相关的错误。 数模转换器（DAC）单元可以被布置为除了二进制输出状态之外还包括一个或多个操作状态，并且可以采用切换技术来在二进制输出之间转储DAC单元。 此外，DAC单元的阵列可以包括用于实现切换技术的部分冗余DAC单元组。

公开(公告)号：US07898329B1

公开(公告)日：2011-03-01

申请号：US12582470

申请日：2009-10-20

申请人： Martin Clara ,  Daniel Gruber ,  Christian Fleischhacker

发明人： Martin Clara ,  Daniel Gruber ,  Christian Fleischhacker

IPC分类号： H03F3/45

CPC分类号： H03G1/0088 ,  H03F3/45475 ,  H03F3/45932 ,  H03F2200/294 ,  H03F2200/411 ,  H03F2200/78 ,  H03G3/3052

摘要： A differential gain stage includes a plurality of programmable passive circuit component arrays operable to set a gain of the gain stage. The gain stage also includes an active switch gate control circuit and a passive switch gate control circuit. The active switch gate control circuit controls a gate voltage applied to transistor switch components of each programmable passive circuit component array as a function of the level of common mode disturbance input to the differential gain stage for common mode frequencies below a particular frequency threshold. The passive switch gate control circuit controls the gate voltage applied to the transistor switch components as a function of the level of common mode disturbance for common mode frequencies above the frequency threshold. The differential gain stage can for part of a receiver such as an xDSL receiver.

摘要翻译： 差分增益级包括多个可编程无源电路组件阵列，可操作以设置增益级的增益。 增益级还包括有源开关门控制电路和无源开关门控制电路。 有源开关栅极控制电路控制施加到每个可编程无源电路组件阵列的晶体管开关组件的栅极电压，作为低于特定频率阈值的共模频率输入到差分增益级的共模干扰电平的函数。 无源开关栅极控制电路控制施加到晶体管开关部件的栅极电压作为高于频率阈值的共模频率的共模干扰电平的函数。 差分增益级可以用于诸如xDSL接收器的接收器的一部分。