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    Method and structure for creating high density buried contact for use with SOI processes for high performance logic
    1.
    发明授权
    Method and structure for creating high density buried contact for use with SOI processes for high performance logic 有权
    用于创建高密度埋地触点的方法和结构，用于高性能逻辑的SOI工艺

    公开(公告)号：US06436744B1

    公开(公告)日：2002-08-20

    申请号：US09809888

    申请日：2001-03-16

    申请人： Andres Bryant ,  Jerome B. Lasky ,  Edward J. Nowak ,  Jed H. Rankin ,  Minh H. Tong

    发明人： Andres Bryant ,  Jerome B. Lasky ,  Edward J. Nowak ,  Jed H. Rankin ,  Minh H. Tong

    IPC分类号： H01L2100

    CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78645

    摘要： A semiconductor device having an SOI FET comprising a silicon body on an insulating layer on a conductive substrate. A gate dielectric and a gate are provided on a surface of the silicon body, and a source and a drain are provided on two sides of the gate. A buried body contact to the substrate conductor is provided below a third side of the gate. The buried body contact does not extend to the top surface of the silicon body. The body contact is separated from the gate by a second dielectric having a thickness typically greater than that of the gate dielectric. The body contact is a plug of conductive material, and the second dielectric coats the body contact under the gate. The FET can be used in an SRAM circuit or other type of circuit having a silicon-on-insulator (SOI) construction.

    摘要翻译： 一种具有SOI FET的半导体器件，其在导电基板上的绝缘层上包括硅体。 栅极电介质和栅极设置在硅体的表面上，源极和漏极设置在栅极的两侧。 在栅极的第三侧的下方设置与基板导体的埋入体接触。 埋体体接触不延伸到硅体的顶表面。 通过具有通常大于栅极电介质的厚度的厚度的第二电介质将体接触件与栅极分离。 身体接触是导电材料的塞子，第二电介质在门下方涂覆身体接触。 该FET可用于具有绝缘体上硅（SOI）结构的SRAM电路或其他类型的电路中。

    Fin field effect transistor with self-aligned gate
    4.
    发明授权
    Fin field effect transistor with self-aligned gate 有权
    具有自对准栅极的Fin场效应晶体管

    公开(公告)号：US06689650B2

    公开(公告)日：2004-02-10

    申请号：US09965288

    申请日：2001-09-27

    申请人： Jeffrey P. Gambino ,  Jerome B. Lasky ,  Jed H. Rankin

    发明人： Jeffrey P. Gambino ,  Jerome B. Lasky ,  Jed H. Rankin

    IPC分类号： H01L2100

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78636

    摘要： The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

    摘要翻译： 本发明提供一种用于制造具有双栅极和双通道的金属氧化物半导体场效应晶体管（MOSFET）的方法，其中栅极区域与沟道区域和源极/漏极扩散接合点自对准。 本发明还涉及使用本发明的方法形成的FIN MOSFFET结构。

    Hot-electron programmable latch for integrated circuit fuse applications and method of programming therefor
    5.
    发明授权
    Hot-electron programmable latch for integrated circuit fuse applications and method of programming therefor 失效
    用于集成电路保险丝应用的热电子可编程锁存器及其编程方法

    公开(公告)号：US06038168A

    公开(公告)日：2000-03-14

    申请号：US105339

    申请日：1998-06-26

    申请人： Archibald J. Allen ,  Jerome B. Lasky ,  John J. Pekarik ,  Jed H. Rankin ,  Francis R. White

    发明人： Archibald J. Allen ,  Jerome B. Lasky ,  John J. Pekarik ,  Jed H. Rankin ,  Francis R. White

    IPC分类号： G11C17/16 ,  G11C17/18 ,  G11C7/00

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： A method and apparatus for conditioning an integrated circuit to always enter a desired operating state when actuated by permanently altering at least one component device. An integrated circuit is provided with at least one component transistor wherein a constant high voltage is applied only once to the drain electrode of the transistor for one predetermined period of time while concurrently a constant voltage lower than the high voltage is applied only once to the gate electrode of the transistor, thus causing a permanent channel hot-electron alteration of a gate oxide of the transistor. The integrated circuit may include a plurality of programmable circuits, each capable of assuming a plurality of readable data states when powered up, and each including a plurality of programmable devices for permanently biasing its corresponding programmable circuit to assume one of the readable states upon subsequent power ups.

    摘要翻译： 一种用于调节集成电路以在通过永久地改变至少一个组件装置致动时始终进入期望操作状态的方法和装置。 集成电路设置有至少一个元件晶体管，其中恒定的高电压仅施加一次到晶体管的漏极一个预定时间段，同时将低于高电压的恒定电压仅施加一次到栅极 电极，从而导致晶体管的栅极氧化物的永久性通道热电子改变。 集成电路可以包括多个可编程电路，每个可编程电路能够在通电时呈现多个可读数据状态，并且每个可编程电路包括多个可编程器件，用于永久地偏置其相应的可编程电路，以在后续电源中呈现可读状态之一 UPS。

    Buried butted contact and method for fabricating
    6.
    发明授权
    Buried butted contact and method for fabricating 失效
    埋地接头和制造方法

    公开(公告)号：US06335272B1

    公开(公告)日：2002-01-01

    申请号：US09637935

    申请日：2000-08-14

    申请人： Archibald Allen ,  Jerome B. Lasky ,  Randy W. Mann ,  Jed H. Rankin ,  Francis R. White

    发明人： Archibald Allen ,  Jerome B. Lasky ,  Randy W. Mann ,  Jed H. Rankin ,  Francis R. White

    IPC分类号： H01L214763

    CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L21/28568

    摘要： A buried butted contact and method for its fabrication are provided which includes a substrate having dopants of a first conductivity type and having shallow trench isolation. Dopants of a second conductivity type are located in the bottom of an opening in said substrate. Ohmic contact is provided between the dopants in the substrate and the low diffusivity dopants that is located on a side wall of the opening. The contact is a metal silicide, metal and/or metal alloy.

    摘要翻译： 提供了一种用于其制造的埋地对接接触和方法，其包括具有第一导电类型的掺杂剂并且具有浅沟槽隔离的衬底。 第二导电类型的掺杂剂位于所述衬底中的开口的底部。 在衬底中的掺杂剂和位于开口的侧壁上的低扩散性掺杂剂之间提供欧姆接触。 接触是金属硅化物，金属和/或金属合金。

    Method for semiconductor fabrication
    10.
    发明授权
    Method for semiconductor fabrication 失效
    半导体制造方法

    公开(公告)号：US6015745A

    公开(公告)日：2000-01-18

    申请号：US80754

    申请日：1998-05-18

    申请人： James W. Adkisson ,  Jerome B. Lasky ,  Paul W. Pastel ,  Jed H. Rankin

    发明人： James W. Adkisson ,  Jerome B. Lasky ,  Paul W. Pastel ,  Jed H. Rankin

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L21/76224 ,  H01L21/7624

    摘要： An SOI semiconductor design methodology enables the implementation of simplified STI processes by the design and formation of a shallow trench isolation frame around an electrically active semiconductor region. The simplified STI processes include the fabrication of a trench by phase edge etching, trench sidewall oxidation, TEOS fill, and, finally a chemical or mechanical polish. The attribute which enables the simple process is that all isolation images can be current minimum or near minimum size, specifically no wider than twice the over-lay tolerance of the technology.

    摘要翻译： SOI半导体设计方法通过在电活性半导体区域周围的浅沟槽隔离框架的设计和形成来实现简化的STI工艺。 简化的STI工艺包括通过相边缘蚀刻，沟槽侧壁氧化，TEOS填充以及最终的化学或机械抛光来制造沟槽。 实现简单过程的属性是所有隔离图像可以是当前最小或接近最小尺寸，特别是不超过技术的叠加公差的两倍。