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公开(公告)号：US20130193513A1
公开(公告)日：2013-08-01
申请号：US13363651
申请日：2012-02-01
IPC分类号： H01L29/786 , G06F17/50 , H01L29/78
CPC分类号： H01L29/785 , H01L29/42376
摘要： A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin.
摘要翻译： 一种多栅极场效应晶体管装置及其制造方法。 该装置包括源极端子，漏极端子和包括锥形栅极形状的栅极端子。 一种用于设计多栅极场效应晶体管的方法包括：设置具有锥形栅极剖面的源极端子，漏极端子和栅极端子，以在散热片的底部产生更宽的栅极宽度。
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公开(公告)号：US08586449B1
公开(公告)日：2013-11-19
申请号：US13603872
申请日：2012-09-05
IPC分类号： H01L21/76
CPC分类号： H01L21/845 , H01L21/76229
摘要： Raised isolation structures can be formed at the same level as semiconductor fins over an insulator layer. A template material layer can be conformally deposited to fill the gaps among the semiconductor fins within each cluster of semiconductor fins on an insulator layer, while the space between adjacent clusters is not filled. After an anisotropic etch, discrete template material portions can be formed within each cluster region, while the buried insulator is physically exposed between cluster regions. A raised isolation dielectric layer is deposited and planarized to form raised isolation structures employing the template material portions as stopping structures. After removal of the template material portions, a cluster of semiconductor fins are located within a trench that is self-aligned to outer edges of the cluster of semiconductor fins. The trench can be employed to confine raised source/drain regions to be formed on the cluster of semiconductor fins.
摘要翻译： 升高的隔离结构可以在与绝缘体层上的半导体鳍片相同的水平上形成。 可以共形沉积模板材料层以填充绝缘体层上的每个半导体翅片簇内的半导体鳍片之间的间隙，而相邻簇之间的空间未被填充。 在各向异性蚀刻之后，可以在每个簇区域内形成离散的模板材料部分，而埋入的绝缘体在簇区域之间物理暴露。 沉积并平坦化凸起的隔离介电层以形成采用模板材料部分作为停止结构的凸起隔离结构。 在去除模板材料部分之后，一组半导体鳍片位于与半导体鳍片簇的外边缘自对准的沟槽内。 沟槽可以用来限制要形成在半导体鳍片簇上的凸起的源极/漏极区域。
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公开(公告)号：US09214529B2
公开(公告)日：2015-12-15
申请号：US13047132
申请日：2011-03-14
CPC分类号： H01L29/66545 , B82Y10/00 , H01L27/1211 , H01L29/66795 , H01L29/7855
摘要： A FinFET device with an independent control gate, including: a silicon-on-insulator substrate; a non-planar multi-gate transistor disposed on the silicon-on-insulator substrate, the transistor comprising a conducting channel wrapped around a thin silicon fin; a source/drain extension region; an independently addressable control gate that is self-aligned to the fin and does not extend beyond the source/drain extension region, the control gate comprising: a thin layer of silicon nitride; and a plurality of spacers.
摘要翻译： 一种具有独立控制栅极的FinFET器件，包括：绝缘体上硅衬底; 设置在绝缘体上硅衬底上的非平面多栅极晶体管，所述晶体管包括围绕薄硅片缠绕的导电沟道; 源极/漏极延伸区域; 独立可寻址的控制栅极，其与所述鳍片自对准并且不延伸超过所述源极/漏极延伸区域，所述控制栅极包括：氮化硅薄层; 和多个间隔件。
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4.发明授权Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices 有权金属门功能工程技术可实现多个阈值电压FINFET器件公开(公告)号：US08669167B1
公开(公告)日：2014-03-11
申请号：US13596687
申请日：2012-08-28
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/845
摘要： Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided.
摘要翻译： 在Fin FET器件中提供栅极功能工程的技术，其功能设定材料的数量与翅片间距成正比。 一方面，制造FIN FET器件的方法包括以下步骤。 提供了在BOX上具有SOI层的SOI晶片。 在SOI层上形成氧化物层。 在SOI层和氧化物层中图案化多个翅片。 翅片上形成界面氧化物。 共形栅介电层，共形栅极金属层和共形功函数设定材料层沉积在散热片上。 共形栅极金属层的体积和沉积在鳍片上的共形功函数设定材料层的体积与翅片的间距成正比。 还提供了一种FIN FET器件。
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5.发明申请Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices 有权金属栅极工作功能工程技术开启多阈值电压纳米线FET器件公开(公告)号：US20140051213A1
公开(公告)日：2014-02-20
申请号：US13588724
申请日：2012-08-17
IPC分类号： H01L21/336
CPC分类号： H01L29/16 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/4232 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.
摘要翻译： 制造纳米线FET器件的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层中蚀刻纳米线和焊盘。 纳米线悬挂在BOX上。 围绕每个纳米线形成界面氧化物。 共形栅电介质沉积在界面氧化物上。 保形第一栅极材料沉积在保形栅极电介质上。 工件功能设定材料沉积在保形第一栅极材料上。 第二栅极材料沉积在功函数设定材料上以在纳米线上形成至少一个栅叠层。 栅极堆叠中的共形第一栅极材料的体积和/或功函数设定材料的体积与纳米线的间距成比例。
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6.发明申请TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES 有权门工功能工程技术降低平面CMOS器件中的短路通道效应公开(公告)号：US20140048882A1
公开(公告)日：2014-02-20
申请号：US13617283
申请日：2012-09-14
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/1203
摘要： In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide on the SOI layer and a gate stack on the interfacial oxide layer, the gate stack having (i) a conformal gate dielectric layer present on a top and sides of the gate stack, (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer lining the conformal gate metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer present in the gate stack are/is proportional to a length of the gate stack.
摘要翻译： 在一个方面，提供一种CMOS器件。 CMOS器件包括在BOX上具有SOI层的SOI晶片; 形成在其中形成有一个或多个FET器件的SOI层中的一个或多个有源区，每个FET器件在SOI层上具有界面氧化物，在界面氧化物层上具有栅极堆叠，所述栅极堆叠具有（i） 存在于栅极堆叠的顶部和侧面上的共形栅极电介质层，（ii）衬在栅极介电层的共形栅极金属层，以及（iii）在保形栅极金属层之上的共形功函数设定金属层。 存在于栅极堆叠中的共形栅极金属层的体积和/或共形功函数设定金属层的体积与栅极堆叠的长度成比例。
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7.发明申请Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure 有权通过使用可变间距门形成的非对称FET用作逻辑器件和测试结构公开(公告)号：US20130256797A1
公开(公告)日：2013-10-03
申请号：US13441048
申请日：2012-04-06
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/823437 , H01L22/34 , H01L27/0207 , H01L27/1203
摘要： Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a FET device is provided. The FET device includes a wafer; a plurality of active areas formed in the wafer; a plurality of gate stacks on the wafer, wherein at least one of the gate stacks is present over each of the active areas, and wherein the gate stacks have an irregular gate-to-gate spacing such that for at least a given one of the active areas a gate-to-gate spacing on a source side of the given active area is greater than a gate-to-gate spacing on a drain side of the given active area; spacers on opposite sides of the gate stacks; and an angled implant in the source side of the given active area.
摘要翻译： 提供了非对称FET器件及其制造方法，其采用可变间距栅极。 一方面，提供一种FET器件。 FET器件包括晶片; 形成在晶片中的多个有源区; 晶片上的多个栅极堆叠，其中至少一个栅极堆叠存在于每个有源区域上，并且其中栅极堆叠具有不规则的栅极至栅极间隔，使得对于至少一个 有源区域在给定有源区域的源极侧上的栅极至栅极间隔大于给定有源区域的漏极侧上的栅极至栅极间隔; 栅极堆叠的相对侧上的间隔物; 以及在给定活动区域的源侧的成角度的植入物。
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公开(公告)号：US08536029B1
公开(公告)日：2013-09-17
申请号：US13529334
申请日：2012-06-21
CPC分类号： H01L21/845 , B82Y10/00 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： A method includes thinning a first region of an active layer, for form a stepped surface in the active layer defined by the first region and a second region of the active layer, depositing an planarizing layer on the active layer that defines a planar surface disposed on the active layer, etching to define nanowires and pads in the first region of the active layer, suspending the nanowires over the BOX layer, etching fins in the second region of the active layer forming a first gate stack that surrounds portion of each of the nanowires, forming a second gate stack covering a portion of the fins, and growing an epitaxial material wherein the epitaxial material defines source and drain regions of the nanowire FET and source and drain regions of the finFET.
摘要翻译： 一种方法包括使有源层的第一区域变薄，以形成由有源层的第一区域和第二区域限定的有源层中的阶梯表面，在活性层上沉积限定平面的平坦化层， 有源层，蚀刻以在有源层的第一区域中限定纳米线和焊盘，将纳米线悬挂在BOX层上，蚀刻有源层的第二区域中的鳍形成围绕每个纳米线的部分的第一栅极堆叠 形成覆盖所述翅片的一部分的第二栅极堆叠，以及生长外延材料，其中所述外延材料限定所述纳米线FET的源极和漏极区域以及所述finFET的源极和漏极区域。
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公开(公告)号：US08426917B2
公开(公告)日：2013-04-23
申请号：US12683606
申请日：2010-01-07
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78612 , H01L21/26586 , H01L29/1083 , H01L29/42384 , H01L29/66772
摘要： In one exemplary embodiment of the invention, an asymmetric P-type field effect transistor includes: a source region coupled to a drain region via a channel; a gate structure overlying at least a portion of the channel; a halo implant disposed at least partially in the channel, where the halo implant is disposed closer to the source region than the drain region; and a body-tie coupled to the channel. In a further exemplary embodiment, the asymmetric P-type field effect transistor is operable to act as a symmetric P-type field effect transistor.
摘要翻译： 在本发明的一个示例性实施例中，非对称P型场效应晶体管包括：源极区，经由沟道耦合到漏极区; 覆盖所述通道的至少一部分的栅极结构; 至少部分地设置在所述通道中的卤素植入物，其中所述晕轮植入物设置成比所述漏极区域更靠近所述源极区域; 以及耦合到该通道的机身连接。 在另一示例性实施例中，非对称P型场效应晶体管可用作对称P型场效应晶体管。
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公开(公告)号：US08338256B2
公开(公告)日：2012-12-25
申请号：US12832829
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/785 , H01L29/66795 , H01L2029/7858
摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
摘要翻译： 一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成 沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。 该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻 沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。
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