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    High-speed digital bus-organized multiplier/divider system
    3.
    发明授权
    High-speed digital bus-organized multiplier/divider system 失效
    高速数字总线组合乘法器/分频器系统

    公开(公告)号：US4238833A

    公开(公告)日：1980-12-09

    申请号：US24540

    申请日：1979-03-28

    申请人： Robert C. Ghest ,  John M. Birkner ,  Shlomo Waser ,  Hua T. Chua

    发明人： Robert C. Ghest ,  John M. Birkner ,  Shlomo Waser ,  Hua T. Chua

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5338 ,  G06F7/535 ,  G06F2207/5352

    摘要： A bus organized 16.times.16 (or 8.times.8) high-speed digital bus-organized multiplier/divider for high-speed, low-power operation is implemented on a single semiconductor chip. Four working registers each of 16 (or 8) bits are used in the system. These registers are a multiplier register, a multiplicand and divisor register, a first accumulator register for storing the least significant half of a double length product after a multiplication of the remainder after a division operation, and a second accumulator register which stores the most significant half of the product after a multiplication or the quotient after a division operation. A decoder is connected to the multiplicand and multiplier registers to implement the Modified Booth Algorithm and to encode the 16 (or 8) multiplier digits. The system operates to shift the multiplier number through the multiplier register to a position where the Modified Booth Algorithm encoding takes place. The Modified Booth encoder then controls the operation of multiplexer circuits to which the outputs of the multiplicand register are applied to produce successive partial products. A carry/save arithmetic logic unit operates in conjunction with the registers to cause accumulation and storage of multiplication products and division quotient/remainders in the double length accumulator registers which provide a 32 bit output number. BACKGROUND OF THE INVENTIONHigh speed digital multipliers and digital dividers have a wide number of applications in digital signal processing. Multiplication or division of binary numbers can be performed in a relatively simply manner. For multiplication, a classic approach is to provide an accumulate register which has twice the length n of the operands, because the product can approach twice the size of the operands. The multiplier is conveniently stored in the less significant half of the accumulator register. The most significant half and the contents of a multiplicand register are applied to an adder. The output of the adder is effectively the sum of the accumulated partial products and the potential partial product consisting of one times the multiplicand. A series of n cycles is set up. For each cycle, the least significant bit of the accumulator is examined; and the output of the adder is stored in the more significant half of the accumulator or not, in accordance with that bit being a binary "1" or a "0", respectively. The accumulator then is shifted to the right one bit, and the cycle is repeated until the entire multiplier has been examined. As a consequence, the multiplicand has been multiplied by 2.sup.n, for every "1" bit in the multiplier; and these partial products have been accumulated with the proper alignment due to the cyclic shifts which divide the result by 2 in each cycle. Various techniques exist in the art for handling different sign combinations of the operands, for the different types of number representations, that is, sign and magnitude, 1's complement and 2's complement.A problem which exists with a digital multiplier of the type just described is that for 16 bit operands, the process calls for 16 cycles to obtain each of the 16 different partial products. These partial products then are added together in an additional 16 adder circuits to obtain the final resultant product, and all of the gates and other circuitry results in dissipation of a substantial amount of power. In addition, as the size of the multiplier increases (for example from an 8.times.8 to a 16.times.16 or a 32.times.32 multiplier), the length of time for accomplishing the multiplication increases in direct proportion.Because of the large number of circuit components which are necessary with such a prior art approach, implementation of large multipliers on a single LSI chip has not proved practical. As a result such circuitry is usually implemented in several chips which must be interconnected together externally to form the complete circuit.Another disadvantage with the standard prior art approaches is the dissipation of relatively large amounts of power, so that it is necessary to employ forced air cooling or other types of cooling during the operation of the system. The resultant machine is correspondingly increased in complexity and cost as a result of the relatively high power dissipation.A solution to some of the problems inherent in the prior art is disclosed in U.S. Pat. No. 4,153,938 issued May 8, 1979 filed on Aug. 18, 1977 and assigned to the same assignee as the present application. In this copending application, a high speed 8.times.8 digital multiplier is implemented in a single LSI chip using circuitry for implementing a Modified Booth Algorithm to examine the binary multiplier 3 bits at a time and shifted 2 bits at a time in sequence for performing the multiplication function. In the copending application, this examination is effected through the use of several Modified Booth encoder gating circuits, each responsive to a different group of 3 bits of the multiplier input register, for controlling the shifting of the outputs of the multiplicand register applied to the input of an array of carry/save adder circuits to effect the desired multiplication. The result is a reduction in the number of cycles required to complete the multiplication operation and a reduction in the circuitry necessary to carry it out, along with reduced power dissipation.It is desirable to implement a 16.times.16 multiplier on a single integrated circuit chip and further to implement a 16.times.16 multiplier/divider system on a single IC chip for high speed operation with minimal power consumption. Other features which are desirable in such multiplier/divider circuits, and which are particularly desirable in circuits implemented in a single integrated circuit chip, are the ability to multiply and accumulate in a single cycle of operation, to perform the entry of new data from the input busses simultaneously with the processing of previous entries, and the multiplication or division of new entries or accumulated entries by a constant.SUMMARY OF THE INVENTIONIt is an object of this invention to provide an improved high-speed digital multiplier.It is another object of this invention to provide an improved high-speed digital multiplier/divider.It is an additional object of this invention to provide a high-speed digital multiplier of at least 16 bits by 16 bits on a single semiconductor chip.It is still another object of the invention to provide a high-speed digital multiplier/divider on a single semiconductor chip having reduced power dissipation.It is still a further object of this invention to provide a bus organized multiplier/divider having a variety of different multiply and divide options controlled by external instruction signals.Yet another object of this invention is to implement a high-speed, low-power dissipation digital multiplier/divider system utilizing circuitry which generates a reduced number of partial products.In accordance with the preferred embodiment of this invention, a digital multiplier circuit includes registers for receiving the multiplier inputs and the multiplicand inputs. A partial product generator coupled to the registers includes an encoder which encodes the multiplier inputs according to the Modified Booth Algorithm to produce control signals which are applied to a plurality of multiplexer circuits interconnecting the multiplicand register with the partial product generating circuitry to produce the resultant number. The information in the multiplier register is shifted on a step-by-step basis through the register to present the contents of the register to the encoder circuitry; so that only a single Modified Booth Algorithm encoder circuit is required, irrespective of the length of the multiplier in the multiplier register.In more specific embodiments of the invention, accumulator registers are provided and the system includes operating mode control circuitry for permitting operation of the system either as a multiplier or as a divider. In addition, a state counter is used in conjunction with external mode control signals applied to the circuit to permit a variety of multiplication and accumulation functions as well as a variety of divider functions to be accomplished by the system. These functions include positive and negative multiplication, positive and negative accumulation, multiplication by a constant, and both single and double length addition in conjunction with mmultiplication, along with divide options including single or double length division, division of a previous generated number, division by a constant, and continual division of a remainder or quotient.

    摘要翻译： 在单个半导体芯片上实现了一个总线，用于高速，低功耗操作的16x16（或8x8）高速数字总线组合乘法器/分频器。 系统中使用16个（或8）位中的每个工作寄存器。 这些寄存器是乘法器寄存器，被乘数和除数寄存器，第一累加器寄存器，用于在除法运算之后的余数相乘之后存储双倍长度乘积的最小有效半，以及存储最高有效半 乘法后的乘积或除法运算后的商。 解码器连接到被乘数和乘法器寄存器以实现修改的布尔算法并对16（或8）个乘法器数字进行编码。 该系统操作以将乘数通过乘数寄存器移动到发生修改展位算法编码的位置。 修改后的编码器然后控制多路复用器电路的操作，多路复用器电路被应用寄存器的输出以产生连续的部分乘积。 进位/保存算术逻辑单元与寄存器一起运行，以使倍增乘积的积累和存储以及提供32位输出数的双倍长度累加器寄存器中的除法/余数。

    Electrically programmable interconnect structure having a PECVD amorphous silicon element
    4.
    发明授权
    Electrically programmable interconnect structure having a PECVD amorphous silicon element 失效
    具有PECVD非晶硅元件的电可编程互连结构

    公开(公告)号：US5502315A

    公开(公告)日：1996-03-26

    申请号：US161504

    申请日：1993-12-02

    申请人： Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

    发明人： Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

    IPC分类号： H01L23/525 ,  H02L27/02

    CPC分类号： H01L23/5252 ,  H01L2924/0002

    摘要： In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

    摘要翻译： 在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。 非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。 在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。 在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。 在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。 选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。 还描述了用于形成具有反熔丝的现场可编程门阵列的方法。

    Programmable array logic cell
    8.
    发明授权
    Programmable array logic cell 失效
    可编程阵列逻辑单元

    公开(公告)号：US4789951A

    公开(公告)日：1988-12-06

    申请号：US864185

    申请日：1986-05-16

    申请人： John M. Birkner ,  Danesh M. Tavana ,  Andrew K. Chan ,  Sing Y. Wong

    发明人： John M. Birkner ,  Danesh M. Tavana ,  Andrew K. Chan ,  Sing Y. Wong

    IPC分类号： H03K19/177 ,  H03K3/037 ,  G06F7/38 ,  H03K19/173

    CPC分类号： H03K3/037

    摘要： A programmable array logic cell 60 including a sum-of-products array having a single OR gate 70 for providing a sum signal, and including an XOR gate 80 for combining the sum signal with a product signal provided by an AND gate 78 from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.

    摘要翻译： 一种可编程阵列逻辑单元60，其包括具有用于提供和信号的单或门70的产品和阵列阵列，并且包括用于将和信号与由和门78从选定阵列提供的乘积信号组合的XOR门80 输入和/或反馈信号。 产品信号可以是用于JK触发器配置的先前状态输出信号Q，或用于可编程输出信号极性的其他配置的强制高或低信号。

    Programmable application specific integrated circuit and logic cell
    9.
    发明授权
    Programmable application specific integrated circuit and logic cell 失效
    可编程专用集成电路和逻辑单元

    公开(公告)号：US6078191A

    公开(公告)日：2000-06-20

    申请号：US38728

    申请日：1998-03-10

    申请人： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

    发明人： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

    IPC分类号： H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

    摘要： A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

    摘要翻译： 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。