公开(公告)号：US20070060059A1

公开(公告)日：2007-03-15

申请号：US11450543

申请日：2006-06-09

申请人： Andrew Kim ,  Edward Gebara ,  Bruce Schmukler ,  Mark Dickmann ,  Michael Farrell ,  Michael Vrazel ,  David Stelliga ,  Joy Laskar ,  Charles Summers

发明人： Andrew Kim ,  Edward Gebara ,  Bruce Schmukler ,  Mark Dickmann ,  Michael Farrell ,  Michael Vrazel ,  David Stelliga ,  Joy Laskar ,  Charles Summers

IPC分类号： H04B1/00 ,  H04B15/00

CPC分类号： H04B1/7103 ,  H04B1/123

摘要： Signals propagating on an aggressor communication channel can cause detrimental interference in a victim communication channel. A signal processing circuit can generate an interference cancellation signal that, when applied to the victim communication channel, cancels the detrimental interference. The signal processing circuit can dynamically adjust or update two or more aspects of the interference cancellation signal, such as an amplitude or gain parameter and a phase or delay parameter. Via the dynamic adjustments, the signal processing circuit can adapt to changing conditions, thereby maintaining an acceptable level of interference cancellation in a fluctuating operating environment. A control circuit that implements the parametric adjustments can have at least two modes of operation, one for adjusting the amplitude parameter and one for adjusting the phase parameter. The modes can be selectable or can be intermittently available, for example.

摘要翻译： 在侵略者通信信道上传播的信号可能对受害者通信信道造成有害的干扰。 信号处理电路可以产生干扰消除信号，当被施加到受害通信信道时，消除有害干扰。 信号处理电路可以动态地调整或更新干扰消除信号的两个或多个方面，例如振幅或增益参数以及相位或延迟参数。 通过动态调整，信号处理电路可以适应变化的条件，从而在波动的操作环境中保持可接受的干扰消除水平。 实现参数调整的控制电路可以具有至少两种操作模式，一种用于调整幅度参数，一种用于调整相位参数。 这些模式可以是可选择的，或者可以间歇地可用。

公开(公告)号：US07269217B2

公开(公告)日：2007-09-11

申请号：US10264359

申请日：2002-10-04

申请人： James William Leith ,  Mark Dickmann

发明人： James William Leith ,  Mark Dickmann

IPC分类号： H03K7/08 ,  H03K9/08

CPC分类号： H03L7/107 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/183

摘要： A pulse-width modulation (PWM) controller to supply power to electronic components using a phase lock loop (PLL) is presented. A PWM controller comprises an input node operable to receive a reference signal and a phase-locked loop (PLL). The PLL comprises an oscillator operable to receive an error-correction signal and to generate an oscillator signal having a frequency that is related to the error-correction signal, a phase-frequency detector (PFD) coupled to the oscillator and operable to receive the reference signal and to generate the error-correction signal based upon a phase difference between the reference signal and a feedback signal, and a suppression circuit coupled to the PFD and operable to periodically enable the PFD to generate the error-correction signal.

摘要翻译： 提出了使用锁相环（PLL）向电子元件供电的脉宽调制（PWM）控制器。 PWM控制器包括可操作以接收参考信号的输入节点和锁相环（PLL）。 PLL包括可操作用于接收纠错信号并产生具有与纠错信号相关的频率的振荡器信号的振荡器，耦合到振荡器并且可操作以接收参考的相位 - 频率检测器（PFD） 信号，并且基于参考信号和反馈信号之间的相位差产生纠错信号，以及耦合到PFD的抑制电路，并且可操作以周期性地使PFD产生纠错信号。

公开(公告)号：US06853252B2

公开(公告)日：2005-02-08

申请号：US10264360

申请日：2002-10-04

申请人： Mark Dickmann

发明人： Mark Dickmann

IPC分类号： G06F1/10 ,  G06F1/26 ,  H03K5/00 ,  H03K23/66 ,  H03L7/07 ,  H03L7/089 ,  H03L7/107 ,  H03L7/183 ,  H03L7/00

CPC分类号： H03K23/66 ,  G06F1/10 ,  G06F1/26 ,  H03K2005/00286 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/107 ,  H03L7/183 ,  Y10S331/02

摘要： A phase-locked loop having a programmable loop bandwidth is provided. A PLL comprises an oscillator operable to receive an error-correction signal and to generate an oscillator signal having a frequency that is related to the error-correction signal. The PLL further comprises a phase-frequency detector (PFD) coupled to the oscillator and operable to receive a reference signal and to generate the error-correction signal based upon a phase difference between the reference signal and a feedback signal derived from the oscillator signal. The PLL further comprises an error-correction signal suppression circuit coupled to the PFD and operable to control the loop bandwidth of the PLL by periodically enabling the PFD.

摘要翻译： 提供了具有可编程环路带宽的锁相环。 PLL包括可操作以接收纠错信号并产生具有与纠错信号相关的频率的振荡器信号的振荡器。 PLL还包括耦合到振荡器的相位频率检测器（PFD），用于接收参考信号并且基于参考信号和从振荡器信号导出的反馈信号之间的相位差产生误差校正信号。 PLL还包括耦合到PFD的纠错信号抑制电路，并且可操作以通过周期性地使能PFD来控制PLL的环路带宽。