公开(公告)号：US20090130803A1

公开(公告)日：2009-05-21

申请号：US12360961

申请日：2009-01-28

申请人： Andrew M. WAITE ,  Scott LUNING

发明人： Andrew M. WAITE ,  Scott LUNING

IPC分类号： H01L21/20

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

摘要： A stressed field effect transistor and methods for its fabrication are provided. The field effect transistor comprises a silicon substrate with a gate insulator overlying the silicon substrate. A gate electrode overlies the gate insulator and defines a channel region in the silicon substrate underlying the gate electrode. A first silicon germanium region having a first thickness is embedded in the silicon substrate and contacts the channel region. A second silicon germanium region having a second thickness greater than the first thickness and spaced apart from the channel region is also embedded in the silicon substrate.

摘要翻译： 提供了一种应力场效应晶体管及其制造方法。 场效应晶体管包括具有覆盖硅衬底的栅极绝缘体的硅衬底。 栅电极覆盖栅极绝缘体，并且在栅电极下面的硅衬底中限定沟道区。 具有第一厚度的第一硅锗区域嵌入在硅衬底中并与沟道区域接触。 具有大于第一厚度并且与沟道区间隔开的第二厚度的第二硅锗区域也嵌入在硅衬底中。

公开(公告)号：US20080261408A1

公开(公告)日：2008-10-23

申请号：US11738828

申请日：2007-04-23

申请人： Andrew M. WAITE ,  Scott LUNING ,  Frank (Bin) Yang

发明人： Andrew M. WAITE ,  Scott LUNING ,  Frank (Bin) Yang

IPC分类号： H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

摘要： A method is provided for fabricating a semiconductor device on a semiconductor substrate. A plurality of narrow gate pitch transistors (NPTs) and wide gate pitch transistors (WPTs) are formed on and in the semiconductor substrate. The NPTs are spaced apart by a first distance, and the WPTs are spaced apart by a second distance greater than the first distance. A first stress liner layer is deposited overlying the NPTs, the WPTs and the semiconductor layer, an etch stop layer is deposited overlying the first stress liner layer, and a second stress liner layer is deposited overlying the etch stop layer. A portion of the second stress liner layer which overlies the WPTs is covered, and an exposed portion of the second stress liner layer which overlies the NPTs is removed to expose an exposed portion of the etch stop layer. The exposed portion of the etch stop layer which overlies the NPTs is removed.

摘要翻译： 提供了一种在半导体衬底上制造半导体器件的方法。 在半导体衬底上形成多个窄栅极间距晶体管（NPT）和宽栅极间距晶体管（WPT）。 NPT间隔开第一距离，并且WPT间隔开大于第一距离的第二距离。 沉积覆盖在NPT，WPT和半导体层上的第一应力衬垫层，沉积覆盖在第一应力衬垫层上的蚀刻停止层，并且沉积覆盖在蚀刻停止层上的第二应力衬垫层。 覆盖在WPT上的第二应力衬垫层的一部分被覆盖，并且去除覆盖在NPT上的第二应力衬垫层的暴露部分以露出蚀刻停止层的暴露部分。 去除覆盖在NPT上的蚀刻停止层的暴露部分。

公开(公告)号：US20110024841A1

公开(公告)日：2011-02-03

申请号：US12904662

申请日：2010-10-14

申请人： Frank Bin YANG ,  Andrew M. WAITE ,  Scott LUNING

发明人： Frank Bin YANG ,  Andrew M. WAITE ,  Scott LUNING

IPC分类号： H01L29/78 ,  H01L25/07

CPC分类号： H01L21/26586 ,  H01L29/66659 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S438/931 ,  H01L2924/00

摘要： A method for fabricating a MOSFET (e.g., a PMOS FET) includes providing a semiconductor substrate having surface characterized by a (110) surface orientation or (110) sidewall surfaces, forming a gate structure on the surface, and forming a source extension and a drain extension in the semiconductor substrate asymmetrically positioned with respect to the gate structure. An ion implantation process is performed at a non-zero tilt angle. At least one spacer and the gate electrode mask a portion of the surface during the ion implantation process such that the source extension and drain extension are asymmetrically positioned with respect to the gate structure by an asymmetry measure.

摘要翻译： 一种用于制造MOSFET（例如，PMOS FET）的方法包括提供具有由（110）表面取向或（110）侧壁表面表征的表面的半导体衬底，在表面上形成栅极结构，并形成源延伸和 半导体衬底中的漏极延伸部相对于栅极结构非对称地定位。 以非零倾角进行离子注入工艺。 在离子注入过程期间，至少一个间隔物和栅电极掩盖表面的一部分，使得源极延伸和漏极延伸通过不对称度量相对于栅极结构不对称地定位。

公开(公告)号：US20110204446A1

公开(公告)日：2011-08-25

申请号：US13098065

申请日：2011-04-29

申请人： Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

发明人： Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

IPC分类号： H01L29/78

CPC分类号： H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

摘要： A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

摘要翻译： 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。

公开(公告)号：US20080220579A1

公开(公告)日：2008-09-11

申请号：US11683174

申请日：2007-03-07

申请人： Rohit PAL ,  David BROWN ,  Scott LUNING

发明人： Rohit PAL ,  David BROWN ,  Scott LUNING

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L29/0847 ,  H01L21/31662 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7848

摘要： According to a method for fabricating a stress enhanced MOS device having a channel region at a surface of a semiconductor substrate, first and second trenches are etched into the semiconductor substrate, the first trench having a first side surface, and the second trench having a second side surface. The first and second side surfaces are formed astride the channel region. The first and second side surfaces are then oxidized in a controlled oxidizing environment to thereby grow an oxide region. The oxide region is then removed, thereby repositioning the first and second side surfaces closer to the channel region. With the first and second side surfaces repositioned, the first and second trenches are filled with SiGe.

摘要翻译： 根据用于制造在半导体衬底的表面具有沟道区的应力增强型MOS器件的方法，第一和第二沟槽被蚀刻到半导体衬底中，第一沟槽具有第一侧表面，并且第二沟槽具有第二沟槽 侧面。 第一和第二侧表面跨越通道区域形成。 然后将第一和第二侧表面在受控的氧化环境中氧化，从而生长氧化物区域。 然后去除氧化物区域，从而将第一和第二侧表面重新定位成更靠近沟道区域。 在第一和第二侧表面重新定位时，第一和第二沟槽被填充有SiGe。

公开(公告)号：US20120171820A1

公开(公告)日：2012-07-05

申请号：US13418114

申请日：2012-03-12

申请人： Andrew Michael WAITE ,  Scott LUNING

发明人： Andrew Michael WAITE ,  Scott LUNING

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method is provided for fabricating a strained MOS device having a silicon germanium on insulator (SGOI) substrate that includes a layer of monocrystalline silicon germanium material characterized by a first lattice constant. A strained silicon layer is formed over the layer of monocrystalline silicon germanium material. A layer of gate electrode material is patterned to form a gate electrode overlying a channel region. The strained silicon layer is disposed between the gate electrode and the channel region. First recess and second recesses are etched into the layer of monocrystalline silicon germanium material. A layer of monocrystalline semiconductor material is then epitaxially grown to fill the first and second recesses such that it is embedded at the opposing sides of the channel region. The layer of monocrystalline semiconductor material comprises silicon and germanium, and is characterized by a second lattice constant less than the first lattice constant.

摘要翻译： 提供了一种用于制造具有绝缘体硅锗（SGOI）衬底的应变MOS器件的方法，其包括以第一晶格常数为特征的单晶硅锗材料层。 在单晶硅锗材料层上形成应变硅层。 图案化栅电极材料层以形成覆盖沟道区的栅电极。 应变硅层设置在栅电极和沟道区之间。 第一凹陷和第二凹陷蚀刻到单晶硅锗材料层中。 然后外延生长一层单晶半导体材料以填充第一和第二凹部，使得其嵌入在沟道区域的相对侧。 单晶半导体材料层包括硅和锗，其特征在于小于第一晶格常数的第二晶格常数。

公开(公告)号：US20110084336A1

公开(公告)日：2011-04-14

申请号：US12576987

申请日：2009-10-09

申请人： Scott LUNING ,  Frank Scott JOHNSON

发明人： Scott LUNING ,  Frank Scott JOHNSON

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

摘要翻译： 提供一种制造半导体器件的方法。 所述方法在半导体衬底上形成翅片布置，所述翅片布置包括一个或多个半导体翅片结构。 该方法通过形成覆盖鳍片布置的栅极布置继续，其中栅极布置包括一个或多个相邻栅极结构。 该方法通过在每个栅极结构的侧壁周围形成外部间隔来进行。 然后使用栅极结构和外部间隔物作为蚀刻掩模来选择性地蚀刻鳍片布置，从而导致栅极结构下面的一个或多个半导体鳍片部分。 该方法通过在一个或多个半导体鳍片部分的侧壁附近形成应力/应变诱导材料来继续。

公开(公告)号：US20110021026A1

公开(公告)日：2011-01-27

申请号：US12509918

申请日：2009-07-27

申请人： Scott LUNING ,  Frank S. Johnson

发明人： Scott LUNING ,  Frank S. Johnson

IPC分类号： H01L21/306

CPC分类号： H01L21/3086 ,  H01L21/845 ,  H01L29/66795

摘要： Methods for fabricating semiconductor structures, such as fin structures of FinFET transistors, are provided. In one embodiment, a method comprises providing a semiconductor substrate and forming a plurality of mandrels overlying the semiconductor substrate. Each of the mandrels has sidewalls. L-shaped spacers are formed about the sidewalls of the mandrels. Each L-shaped spacer comprises a rectangular portion disposed at a base of a mandrel and an orthogonal portion extending from the rectangular portion. Each L-shaped spacer also has a spacer width. The orthogonal portions are removed from each of the L-shaped spacers leaving at least a portion of the rectangular portions. The semiconductor substrate is etched to form fin structures, each fin structure having a width substantially equal to the spacer width.

摘要翻译： 提供了制造半导体结构的方法，例如FinFET晶体管的鳍结构。 在一个实施例中，一种方法包括提供半导体衬底并形成覆盖半导体衬底的多个心轴。 每个心轴都有侧壁。 围绕心轴的侧壁形成L形间隔物。 每个L形间隔件包括设置在心轴的基部和从矩形部分延伸的正交部分的矩形部分。 每个L形间隔物也具有间隔物宽度。 从每个L形间隔件中取出正交部分，留下矩形部分的至少一部分。 蚀刻半导体衬底以形成鳍结构，每个鳍结构的宽度基本上等于间隔物宽度。

公开(公告)号：US20100059852A1

公开(公告)日：2010-03-11

申请号：US12209056

申请日：2008-09-11

申请人： Rohit PAL ,  David BROWN ,  Scott LUNING

发明人： Rohit PAL ,  David BROWN ,  Scott LUNING

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device structure is provided. The method begins by providing a substrate having a layer of semiconductor material, a pad oxide layer overlying the layer of semiconductor material, and a pad nitride layer overlying the pad oxide layer. The method proceeds by selectively removing a portion of the pad nitride layer, a portion of the pad oxide layer, and a portion of the layer of semiconductor material to form an isolation trench. Then, the isolation trench is filled with a lower layer of isolation material, a layer of etch stop material, and an upper layer of isolation material, such that the layer of etch stop material is located between the lower layer of isolation material and the upper layer of isolation material. The layer of etch stop material protects the underlying isolation material during subsequent fabrication steps.

摘要翻译： 提供一种制造半导体器件结构的方法。 该方法开始于提供具有半导体材料层的衬底，覆盖在半导体材料层上的衬垫氧化物层和覆盖衬垫氧化物层的衬垫氮化物层。 该方法通过选择性地去除衬垫氮化物层的一部分，衬垫氧化物层的一部分和半导体材料层的一部分来形成隔离沟槽。 然后，隔离沟槽填充有较低层的隔离材料，一层蚀刻停止材料和上层隔离材料，使得该蚀刻停止材料层位于隔离材料的下层和上部隔离层之间 隔离材料层。 蚀刻停止材料层在随后的制造步骤期间保护下面的隔离材料。

公开(公告)号：US20090256201A1

公开(公告)日：2009-10-15

申请号：US12100598

申请日：2008-04-10

申请人： Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

发明人： Frank Bin YANG ,  Rohit PAL ,  Scott LUNING

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

摘要： A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

摘要翻译： 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。