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1.发明申请PROCESSORS HAVING FULLY-CONNECTED INTERCONNECTS SHARED BY VECTOR CONFLICT INSTRUCTIONS AND PERMUTE INSTRUCTIONS 审中-公开具有由VECTOR CONFLICT指令和指令说明共享的完全连接的互连的处理程序公开(公告)号：US20140181466A1
公开(公告)日：2014-06-26
申请号：US13977126
申请日：2011-12-29
摘要： An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least one source vector. The fully-connected interconnect has at least four outputs. Each of the at least four inputs is coupled with each of the at least four outputs. The execution unit also includes a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to the permute instruction. The execution unit also includes a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to the vector conflict instruction.
摘要翻译： 一种装置包括解码单元，用于解码置换指令和向量冲突指令。 向量执行单元与解码单元耦合并且包括完全连接的互连。 完全连接的互连具有至少四个输入以接收至少一个源向量的至少四个对应的数据元素。 完全连接的互连至少有四个输出。 所述至少四个输入中的每一个与所述至少四个输出中的每一个耦合。 所述执行单元还包括与所述至少四个输出耦合的置换指令执行逻辑，并且可操作以响应于所述置换指令来存储第一向量结果。 执行单元还包括与至少四个输出耦合的向量冲突指令执行逻辑，并且可操作以响应于向量冲突指令将第二向量结果存储在目的地存储位置。
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公开(公告)号：US20130305020A1
公开(公告)日：2013-11-14
申请号：US13976707
申请日：2011-09-30
申请人： Robert C. Valentine , Jesus Corbal San Adrian , Roger Espasa Sans , Robert D. Cavin , Bret L. Toll , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Edward Thomas Grochowski , Jonathan Cannon Hall , Dennis R. Bradford , Elmoustapha Ould-Ahmed-Vall , James C. Abel , Mark Charney , Seth Abraham , Suleyman Sair , Andrew Thomas Forsyth , Lisa Wu , Charles Yount
发明人： Robert C. Valentine , Jesus Corbal San Adrian , Roger Espasa Sans , Robert D. Cavin , Bret L. Toll , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Edward Thomas Grochowski , Jonathan Cannon Hall , Dennis R. Bradford , Elmoustapha Ould-Ahmed-Vall , James C. Abel , Mark Charney , Seth Abraham , Suleyman Sair , Andrew Thomas Forsyth , Lisa Wu , Charles Yount
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30047 , G06F9/30149 , G06F9/30181 , G06F9/30185 , G06F9/30192 , G06F9/34
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
摘要翻译： 一种向量友好的指令格式及其执行。 根据本发明的一个实施例，处理器被配置为执行指令集。 指令集包括向量友好指令格式。 向量友好指令格式具有多个字段，包括基本操作字段，修改字段，增加操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同的扩充操作， 基本操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中只有一个不同的值可以被放置在基本操作字段，修饰符字段， 在指令流中的第一指令格式的指令的每次出现时的alpha字段，β字段和数据元素宽度字段。
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3.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK 审中-公开使用WRITEMASK将两个源操作混合到单个目的地的系统，设备和方法公开(公告)号：US20120254588A1
公开(公告)日：2012-10-04
申请号：US13078864
申请日：2011-04-01
申请人： Jesus Corbal San Adrian , Bret L. Toll , Robert C. Valentine , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Andrew Thomas Forsyth , Elmoustapha Ould-Ahmed-Vall , Dennis R. Bradford , Lisa K. Wu
发明人： Jesus Corbal San Adrian , Bret L. Toll , Robert C. Valentine , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Andrew Thomas Forsyth , Elmoustapha Ould-Ahmed-Vall , Dennis R. Bradford , Lisa K. Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/30192 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043
摘要： Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.
摘要翻译： 描述了用于在计算机处理器中执行混合指令的系统，装置和方法的实施例。 在一些实施例中，混合指令的执行使用作为第一操作数和第二操作数之间的选择器的写入掩码的相应比特位置，逐个元素地选择第一和第二源操作数的数据元素，并存储所选择的 数据元素到达目的地的目标位置。
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公开(公告)号：US10678541B2
公开(公告)日：2020-06-09
申请号：US13977126
申请日：2011-12-29
摘要： An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least one source vector. The fully-connected interconnect has at least four outputs. Each of the at least four inputs is coupled with each of the at least four outputs. The execution unit also includes a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to the permute instruction. The execution unit also includes a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to the vector conflict instruction.
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公开(公告)号：US20140149724A1
公开(公告)日：2014-05-29
申请号：US14170397
申请日：2014-01-31
申请人： Robert C. Valentine , Jesus Corbal San Adrian , Roger Espasa Sans , Robert D. Cavin , Bret L. Toll , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Edward Thomas Grochowski , Jonathan Cannon Hall , Dennis R. Bradford , Elmoustapha Ould-Ahmed-Vall , James C. Abel , Mark Charney , Seth Abraham , Suleyman Sair , Andrew Thomas Forsyth , Lisa Wu , Charles Yount
发明人： Robert C. Valentine , Jesus Corbal San Adrian , Roger Espasa Sans , Robert D. Cavin , Bret L. Toll , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Edward Thomas Grochowski , Jonathan Cannon Hall , Dennis R. Bradford , Elmoustapha Ould-Ahmed-Vall , James C. Abel , Mark Charney , Seth Abraham , Suleyman Sair , Andrew Thomas Forsyth , Lisa Wu , Charles Yount
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30149 , G06F9/30185 , G06F9/30192 , G06F9/34
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
摘要翻译： 一种向量友好的指令格式及其执行。 根据本发明的一个实施例，处理器被配置为执行指令集。 指令集包括向量友好指令格式。 向量友好指令格式具有多个字段，包括基本操作字段，修改字段，增加操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同的扩充操作， 基本操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中只有一个不同的值可以被放置在基本操作字段，修饰符字段， 在指令流中的第一指令格式的指令的每次出现时的alpha字段，β字段和数据元素宽度字段。
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6.发明授权公开(公告)号：US08533436B2
公开(公告)日：2013-09-10
申请号：US12492652
申请日：2009-06-26
申请人： Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
发明人： Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
CPC分类号： G06F9/30185 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3861 , G06F12/0817
摘要： In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，一种方法包括在处理器核心中接收用于解码的指令，并且基于是否预测争用来动态地处理具有多种行为之一的指令。 如果没有预测到竞争，则在核心中执行指令，并且如果竞争是预测与指令相关联的数据被编组并发送到所选择的远程代理执行。 描述和要求保护其他实施例。
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公开(公告)号：US08601242B2
公开(公告)日：2013-12-03
申请号：US12653800
申请日：2009-12-18
IPC分类号： G06F9/00
CPC分类号： G06F9/3004 , G06F9/30087
摘要： A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange operation as well as a cache line mark operation that enables the fast compare-exchange operation.
摘要翻译： 公开了一种执行快速比较交换操作的技术。 更具体地，描述了实现快速比较交换操作以及启用快速比较交换操作的高速缓存行标记操作的机器可读介质，处理器和系统。
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8.发明申请SYSTEMS, APPARATUSES, AND METHODS FOR EXPANDING A MEMORY SOURCE INTO A DESTINATION REGISTER AND COMPRESSING A SOURCE REGISTER INTO A DESTINATION MEMORY LOCATION 审中-公开用于将存储源扩展到目标寄存器并将源地址注册到目标存储器位置的系统，装置和方法公开(公告)号：US20120254592A1
公开(公告)日：2012-10-04
申请号：US13078896
申请日：2011-04-01
申请人： Jesus Corbal San Adrian , Roger Espasa Sans , Robert C. Valentine , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Andrew Thomas Forsyth , Victor W. Lee
发明人： Jesus Corbal San Adrian , Roger Espasa Sans , Robert C. Valentine , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Andrew Thomas Forsyth , Victor W. Lee
IPC分类号： G06F9/30
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043
摘要： Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored.
摘要翻译： 描述了用于在计算机处理器中执行展开和/或压缩指令的系统，装置和方法的实施例。 在一些实施例中，扩展指令的执行导致根据写入掩码的值来稀疏地存储在目的地的源的元素的选择，并将源的每个选择的数据元素作为稀疏数据元素存储到目的地 位置，其中目的地位置对应于指示要存储源的相应数据元素的每个写入位位置。
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公开(公告)号：US20110154000A1
公开(公告)日：2011-06-23
申请号：US12653800
申请日：2009-12-18
CPC分类号： G06F9/3004 , G06F9/30087
摘要： A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange operation as well as a cache line mark operation that enables the fast compare-exchange operation.
摘要翻译： 公开了一种执行快速比较交换操作的技术。 更具体地，描述了实现快速比较交换操作以及启用快速比较交换操作的高速缓存行标记操作的机器可读介质，处理器和系统。
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公开(公告)号：US20100332801A1
公开(公告)日：2010-12-30
申请号：US12492652
申请日：2009-06-26
申请人： Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
发明人： Joshua B. Fryman , Edward T. Grochowski , Toni Juan , Andrew Thomas Forsyth , John Mejia , Ramacharan Sundararaman , Eric Sprangle , Roger Espasa , Ravi Rajwar
IPC分类号： G06F9/30
CPC分类号： G06F9/30185 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3861 , G06F12/0817
摘要： In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，一种方法包括在处理器核心中接收用于解码的指令，并且基于是否预测争用来动态地处理具有多种行为之一的指令。 如果没有预测到竞争，则在核心中执行指令，并且如果竞争是预测与指令相关联的数据被编组并发送到所选择的远程代理执行。 描述和要求保护其他实施例。
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