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公开(公告)号：US20070211534A1
公开(公告)日：2007-09-13
申请号：US11684052
申请日：2007-03-09
CPC分类号： G11C29/50 , G11C16/04 , G11C16/10 , G11C29/50004 , G11C29/50016
摘要： The method for programming/erasing a non volatile memory cell device includes at least one electric stress step to apply, to at least one active oxide layer of at least one memory cell of the device, a stress electric field able to remove at least a part of charges trapped in the active oxide layer. The method may be used for devices with floating gate type memory cells. The electric stress step may include the application, to one or more terminals of at least one memory cell, of potentials able to produce an electric field on a corresponding active oxide layer.
摘要翻译： 用于编程/擦除非易失性存储单元器件的方法包括至少一个电应力步骤，以将至少一个该器件的至少一个存储单元的活性氧化物层应用于能够去除至少一部分的应力电场 的电荷被捕获在活性氧化物层中。 该方法可用于具有浮动栅型存储单元的器件。 电应力步骤可以包括向至少一个存储器单元的一个或多个端子施加能够在相应的活性氧化物层上产生电场的电位。
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2.发明申请Method for programming a memory device suitable to minimize the lateral coupling effects between memory cells 有权用于编程适于最小化存储器单元之间的横向耦合效应的存储器件的方法公开(公告)号：US20060203544A1
公开(公告)日：2006-09-14
申请号：US11348513
申请日：2006-02-06
申请人： Angelo Visconti , Mauro Bonanomi
发明人： Angelo Visconti , Mauro Bonanomi
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/10 , G11C16/3404 , G11C16/3427
摘要： A method programs a memory device that includes at least one memory cell matrix. The programming method the steps of: erasing the memory cells; soft programming the memory cells; and complete programming of a group of such memory cells each of them storing its own logic value. Advantageously, the first complete programming step of a group of such memory cells involves cells belonging to a block (A) of the matrix being electrically insulated from the rest of the matrix. A memory device suitable to implement the proposed method is also described.
摘要翻译： 一种方法对包括至少一个存储单元矩阵的存储器件进行编程。 编程方法的步骤：擦除存储单元; 软编程存储单元; 以及一组这样的存储器单元的完整编程，每个这样的存储器单元存储其自己的逻辑值。 有利地，一组这样的存储器单元的第一完整编程步骤涉及属于矩阵的块（A）的单元与矩阵的其余部分电绝缘。 还描述了适于实现所提出的方法的存储器件。
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3.发明授权Method for programming a memory device suitable to minimize the lateral coupling effects between memory cells 有权用于编程适于最小化存储器单元之间的横向耦合效应的存储器件的方法公开(公告)号：US07471571B2
公开(公告)日：2008-12-30
申请号：US11348513
申请日：2006-02-06
申请人： Angelo Visconti , Mauro Bonanomi
发明人： Angelo Visconti , Mauro Bonanomi
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C11/5628 , G11C16/10 , G11C16/3404 , G11C16/3427
摘要： A method programs a memory device that includes at least one memory cell matrix. The programming method the steps of: erasing the memory cells; soft programming the memory cells; and complete programming of a group of such memory cells each of them storing its own logic value. Advantageously, the first complete programming step of a group of such memory cells involves cells belonging to a block (A) of the matrix being electrically insulated from the rest of the matrix. A memory device suitable to implement the proposed method is also described.
摘要翻译： 一种方法对包括至少一个存储单元矩阵的存储器件进行编程。 编程方法的步骤：擦除存储单元; 软编程存储单元; 并且一组这样的存储器单元的完整编程，每个这样的存储器单元存储其自己的逻辑值。 有利地，一组这样的存储器单元的第一完整编程步骤涉及属于矩阵的块（A）的单元与矩阵的其余部分电绝缘。 还描述了适用于实现所提出的方法的存储器件。
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公开(公告)号：US20100140488A1
公开(公告)日：2010-06-10
申请号：US12329740
申请日：2008-12-08
IPC分类号： G01T1/02
CPC分类号： G01T1/026 , G01T1/00 , H01L31/115 , H04N5/357
摘要： A two-dimensional array of memory cells may be used to implement a spatial dosimeter. The two-dimensional array of cells may be implemented by an integrated circuit memory Because of the relatively small size of the integrated circuit memory, the resolution of the resulting array may be less than 100 nanometers. The change in threshold voltage of each of the cells, as a result of radiation exposure, may be used to calculate the dose seen at each cell, allowing dose profiles in two dimensions with sub-micrometer resolution.
摘要翻译： 存储器单元的二维阵列可以用于实现空间剂量计。 单元的二维阵列可以由集成电路存储器实现由于集成电路存储器的尺寸相对较小，所得阵列的分辨率可能小于100纳米。 作为辐射暴露的结果，每个细胞的阈值电压的变化可用于计算在每个细胞处观察到的剂量，允许二维尺度下的亚微米分辨率的剂量分布。
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公开(公告)号：US08791418B2
公开(公告)日：2014-07-29
申请号：US12329740
申请日：2008-12-08
IPC分类号： G01T1/02 , H04N5/357 , H01L31/115
CPC分类号： G01T1/026 , G01T1/00 , H01L31/115 , H04N5/357
摘要： A two-dimensional array of memory cells may be used to implement a spatial dosimeter. The two-dimensional array of cells may be implemented by an integrated circuit memory. Because of the relatively small size of the integrated circuit memory, the resolution of the resulting array may be less than 100 nanometers. The change in threshold voltage of each of the cells, as a result of radiation exposure, may be used to calculate the dose seen at each cell, allowing dose profiles in two dimensions with sub-micrometer resolution.
摘要翻译： 存储器单元的二维阵列可以用于实现空间剂量计。 单元的二维阵列可以由集成电路存储器来实现。 由于集成电路存储器的尺寸相对较小，所得阵列的分辨率可能小于100纳米。 作为辐射暴露的结果，每个细胞的阈值电压的变化可用于计算在每个细胞处观察到的剂量，允许二维尺度下的亚微米分辨率的剂量分布。
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公开(公告)号：US20050230739A1
公开(公告)日：2005-10-20
申请号：US10926785
申请日：2004-08-26
申请人： Mauro Bonanomi
发明人： Mauro Bonanomi
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115
摘要： A CAM memory cellintegrated on a semiconductor substrateincludes a plurality of floating gate memory cells, matrix-organized in rows, called word lines, and columns, called bit lines. The cells belonging to a same row and have floating gate electrodes are short-circuited with each other in order to form a single floating gate electrodefor the CAM memory cell. Advantageously, the single floating gate electrodeis equipped with at least a cavity manufactured in at least a side wall of the single floating gate electrode. A process for manufacturing CAM memory cellsintegrated on a semiconductor substrateis also described.
摘要翻译： 集成在半导体衬底上的CAM存储单元包括多个浮动栅极存储器单元，矩阵组织成行，称为字线和称为位线的列。 属于同一行且具有浮置栅电极的单元彼此短路，以形成用于CAM存储单元的单个浮置栅电极。 有利地，单个浮栅极配备有至少在单个浮栅电极的至少侧壁中制造的空腔。 还描述了用于制造半导体衬底上整合的CAM存储器单元的工艺。
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公开(公告)号：US07285816B2
公开(公告)日：2007-10-23
申请号：US10926785
申请日：2004-08-26
申请人： Mauro Bonanomi
发明人： Mauro Bonanomi
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115
摘要： A CAM memory cell integrated on a semiconductor substrate includes a plurality of floating gate memory cells, matrix-organized in rows, called word lines, and columns, called bit lines. The cells belonging to a same row and have floating gate electrodes are short-circuited with each other in order to form a single floating gate electrode for the CAM memory cell. Advantageously, the single floating gate electrode is equipped with at least a cavity manufactured in at least a side wall of the single floating gate electrode. A process for manufacturing CAM memory cells integrated on a semiconductor substrate is also described.
摘要翻译： 集成在半导体衬底上的CAM存储单元包括被称为位线的多个浮动栅极存储单元，矩阵组织成行，称为字线和列。 属于同一行且具有浮置栅电极的单元彼此短路，以形成用于CAM存储单元的单个浮栅电极。 有利地，单个浮栅电极配备有至少在单个浮栅电极的至少侧壁中制造的空腔。 还描述了集成在半导体衬底上的CAM存储单元的制造工艺。
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