公开(公告)号：US20050245063A1

公开(公告)日：2005-11-03

申请号：US10709357

申请日：2004-04-29

申请人： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

发明人： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01P11/00

CPC分类号： H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

摘要翻译： 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。

公开(公告)号：US20060197119A1

公开(公告)日：2006-09-07

申请号：US11164765

申请日：2005-12-05

申请人： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

发明人： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

IPC分类号： H01L29/80

CPC分类号： H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

摘要： A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

摘要翻译： 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料之上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。

公开(公告)号：US20050062137A1

公开(公告)日：2005-03-24

申请号：US10665993

申请日：2003-09-18

申请人： Raminderpal Singh ,  Youri Tretiakov ,  Kunal Vaed ,  Wayne Woods

发明人： Raminderpal Singh ,  Youri Tretiakov ,  Kunal Vaed ,  Wayne Woods

IPC分类号： H01L27/04 ,  H01L21/82 ,  H01L21/822 ,  H01L23/522 ,  H01L23/66 ,  H01P3/02 ,  H01L29/40 ,  H01L39/00

CPC分类号： H01L23/66 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A vertically stacked coplanar transmission line structure for an IC (integrated circuit) is provided which has superior loss and reflection characteristics relative to conventional on-chip transmission line designs. A simple embodiment of the vertically stacked coplanar transmission line structure comprises a micro-strip pair of first and second vertically stacked coplanar conductors, each comprising a metal layer, a next metal layer down, and an intermediate connecting via layer in between the metal layer and the next metal layer down.

摘要翻译： 提供了一种用于IC（集成电路）的垂直堆叠的共面传输线结构，其相对于传统的片上传输线设计具有优异的损耗和反射特性。 垂直层叠的共面传输线结构的简单实施例包括第一和第二垂直堆叠的共平面导体的微带对，每个包括金属层，下一个金属层，以及金属层和金属层之间的中间连接通孔层 下一个金属层下来。

公开(公告)号：US20060072257A1

公开(公告)日：2006-04-06

申请号：US10954672

申请日：2004-09-30

申请人： Rachel Gordin ,  David Goren ,  Sue Strang ,  Kurt Tallman ,  Youri Tretiakov

发明人： Rachel Gordin ,  David Goren ,  Sue Strang ,  Kurt Tallman ,  Youri Tretiakov

IPC分类号： H02H9/00

CPC分类号： H01L23/528 ,  H01L21/7684 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： An critical interconnect line (300) for an integrated circuit is provided in which the problem of dishing of copper is addressed. An interconnect line (300) is provided for an integrated circuit in the form of a critical interconnect line modelled as a transmission line. The interconnect line (300) is formed of a conductive material having a width (302) and a length (303). The interconnect line (300) comprises at least two fingers (304, 305, 306) extending the length (303) of the interconnect line (300), an elongate aperture (309) in the conductive material separating two adjacent fingers (304, 305, 306), and one or more bridges (308) joining the fingers (304, 305, 306) at intervals along the length (303) of the interconnect line (300). The fingers (303, 304, 305) are kept within a width for which the effect of dishing acceptable width whilst the bridges (307, 308) keep the fingers (304, 305, 306) at the same potential difference.

摘要翻译： 提供了一种用于集成电路的关键互连线（300），其中解决了铜的凹陷问题。 为以建模为传输线的关键互连线的形式的集成电路提供互连线（300）。 互连线（300）由具有宽度（302）和长度（303）的导电材料形成。 互连线（300）包括延伸互连线（300）的长度（303）的至少两个指状物（304,305,306），导电材料中的细长孔（309），分隔两个相邻的指状物（304,305 ，306）和沿着所述互连线（300）的长度（303）的间隔连接所述指状物（304,305,306）的一个或多个桥接器（308）。 手指（303,304,305）保持在一个宽度内，当桥接器（307,308）将手指（304,305,306）保持在相同的电位差时，凹槽可接受宽度的影响。

公开(公告)号：US20060015276A1

公开(公告)日：2006-01-19

申请号：US10710511

申请日：2004-07-16

申请人： David Goren ,  John Katzenstein ,  Youri Tretiakov

发明人： David Goren ,  John Katzenstein ,  Youri Tretiakov

IPC分类号： G01R27/00

CPC分类号： G06F17/5036

摘要： A method for determining fringing capacitances on passive devices within an integrated circuit is disclosed. A fringing capacitance region on a passive device is initially divided into a group of fringing electric field areas. A set of fringing capacitance equations is then developed for the fringing electric field areas accordingly. A determination is made as to whether or not an accuracy of the fringing capacitance equations meets a predetermined threshold. If the accuracy of the fringing capacitance equations meets the predetermined threshold, then the fringing capacitance equations are utilized in compact device models to determine fringing capacitance on the passive device. If the accuracy of the fringing capacitance equations does not meet the predetermined threshold, the physically-based fringing capacitance equations are fitted to a set of extracted data to generate a refined set of physically-based fringing capacitance equations, and the refined set of physically-based fringing capacitance equations is utilized in compact device models to determine fringing capacitance on the passive device.

摘要翻译： 公开了一种用于确定集成电路内无源器件边缘电容的方法。 无源器件上的边缘电容区域最初分为一组边缘电场区域。 然后针对边缘电场区域开发一组边缘电容方程。 确定边缘电容方程的精度是否满足预定阈值。 如果边缘电容方程的精度满足预定阈值，则在紧凑型器件模型中使用边缘电容方程来确定无源器件上的边缘电容。 如果边缘电容方程的精度不满足预定阈值，则基于物理的边缘电容方程拟合到一组提取的数据，以产生精细的基于物理的边缘电容方程组， 在紧凑型设备模型中使用基于边缘的电容方程来确定无源器件上的边缘电容。