公开(公告)号：US07485964B2

公开(公告)日：2009-02-03

申请号：US11399579

申请日：2006-04-06

Applicant: John M. Cotte ,  Kenneth John McCullough ,  Wayne Martin Moreau ,  Kevin Petrarca ,  John P. Simons ,  Charles J. Taft ,  Richard Volant

Inventor： John M. Cotte ,  Kenneth John McCullough ,  Wayne Martin Moreau ,  Kevin Petrarca ,  John P. Simons ,  Charles J. Taft ,  Richard Volant

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/02118 ,  H01L21/0212 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/31695 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/249978 ,  Y10T428/24999 ,  H01L2924/00

Abstract: A dielectric material formed by contacting a low dielectric constant polymer with liquid or supercritical carbon dioxide, under thermodynamic conditions which maintain the carbon dioxide in the liquid or supercritical state, wherein a porous product is formed. Thereupon, thermodynamic conditions are changed to ambient wherein carbon dioxide escapes from the pores and is replaced with air.

Abstract translation: 在将二氧化碳保持在液态或超临界状态的热力学条件下，通过使低介电常数聚合物与液体或超临界二氧化碳接触而形成的电介质材料，其中形成多孔产品。 因此，热力学条件改变为环境，其中二氧化碳从孔中逸出并被空气替代。

公开(公告)号：US20060124927A1

公开(公告)日：2006-06-15

申请号：US10905013

申请日：2004-12-09

Applicant: Robert Groves ,  Peter Gruber ,  Kevin Petrarca ,  Richard Volant ,  George Walker

Inventor： Robert Groves ,  Peter Gruber ,  Kevin Petrarca ,  Richard Volant ,  George Walker

IPC: H01L21/66 ,  H01L23/58

CPC classification number: H05K3/3468 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01066 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K3/325 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  H05K2203/162 ,  H05K2203/167 ,  H01L2224/0401

Abstract: Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.

Abstract translation: 公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。 导电结构包括通过注射成型的焊料形成的高纵横比结构。 本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。 该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。 此外，该方法可以向后兼容并可定制。

公开(公告)号：US20070181974A1

公开(公告)日：2007-08-09

申请号：US11307404

申请日：2006-02-06

Applicant: Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

Inventor： Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

IPC: H01L29/00 ,  H01L21/20

CPC classification number: H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.

Abstract translation: 公开了避免半导体器件小型化的问题的电阻器及相关方法。 在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。 在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。 这两个实施方案可以单独使用或一起使用。 还公开了用于产生电阻器的相关方法。

公开(公告)号：US20060081981A1

公开(公告)日：2006-04-20

申请号：US11271760

申请日：2005-11-10

Applicant: Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

Inventor： Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

公开(公告)号：US20050245063A1

公开(公告)日：2005-11-03

申请号：US10709357

申请日：2004-04-29

Applicant: Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

Inventor： Anil Chinthakindi ,  Robert Groves ,  Youri Tretiakov ,  Kunal Vaed ,  Richard Volant

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01P11/00

CPC classification number: H01P11/003 ,  H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/53238 ,  H01L2223/6622 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

Abstract translation: 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。

公开(公告)号：US20050242373A1

公开(公告)日：2005-11-03

申请号：US11175094

申请日：2005-07-05

Applicant: David Ahlgren ,  Gregory Freeman ,  Marwan Khater ,  Richard Volant

Inventor： David Ahlgren ,  Gregory Freeman ,  Marwan Khater ,  Richard Volant

IPC: H01L21/28 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/737 ,  H01L31/072

CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

Abstract: The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do not include a self-aligned silicide and a self-aligned emitter contact border. The present invention also is related to methods of fabricating the inventive bipolar transistor structure. In the methods of the present invention, a block emitter polysilicon region replaces a conventional T-shaped emitter polysilicon.

Abstract translation: 本发明提供一种具有凸起的非本征基极硅化物和自对准的发射极接触边界的双极晶体管。 与不包括自对准硅化物和自对准发射极接触边界的双极晶体管相比，本发明的双极晶体管表现出减小的寄生效应。 本发明还涉及制造本发明的双极晶体管结构的方法。 在本发明的方法中，块状发射极多晶硅区域代替常规的T形发射极多晶硅。

公开(公告)号：US20050167780A1

公开(公告)日：2005-08-04

申请号：US10768773

申请日：2004-01-29

Applicant: Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

Inventor： Daniel Edelstein ,  Panayotis Andricacos ,  John Cotte ,  Hariklia Deligianni ,  John Magerlein ,  Kevin Petrarca ,  Kenneth Stein ,  Richard Volant

IPC: H01F41/04 ,  H01F17/00 ,  H01L21/02 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/08 ,  H01L23/48 ,  H01L21/8222

CPC classification number: H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

Abstract translation: 一种电感器及其形成方法和电感器，所述方法包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成电介质层; （c）在介电层中形成下沟槽; （d）在介电层的顶表面上形成抗蚀剂层; （e）在所述抗蚀剂层中形成上沟槽，所述上沟槽对准所述下沟槽，所述上沟槽的底部通向所述下沟槽; 和（f）用导体完全填充下沟槽至少部分地填充上沟槽，以形成电感器。 所述电感器包括顶表面，底表面和侧壁，所述电感器的下部将固定距离延伸到形成在半导体衬底上的电介质层和在所述电介质层上方延伸的上部; 以及用于电接触所述电感器的装置。

公开(公告)号：US20050121748A1

公开(公告)日：2005-06-09

申请号：US10727945

申请日：2003-12-04

Applicant: David Ahlgren ,  Gregory Freeman ,  Marwan Khater ,  Richard Volant

Inventor： David Ahlgren ,  Gregory Freeman ,  Marwan Khater ,  Richard Volant

IPC: H01L21/28 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/737 ,  H01L27/082

CPC classification number: H01L29/66287 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/7378

Abstract: The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do not include a self-aligned silicide and a self-aligned emitter contact border. The present invention also is related to methods of fabricating the inventive bipolar transistor structure. In the methods of the present invention, a block emitter polysilicon region replaces a conventional T-shaped emitter polysilicon.

公开(公告)号：US06800503B2

公开(公告)日：2004-10-05

申请号：US10300520

申请日：2002-11-20

Applicant: Joseph T. Kocis ,  James Tornello ,  Kevin S. Petrarca ,  Richard Volant ,  Seshadri Subbanna

Inventor： Joseph T. Kocis ,  James Tornello ,  Kevin S. Petrarca ,  Richard Volant ,  Seshadri Subbanna

IPC: H01L2100

CPC classification number: B81C1/00666 ,  B81B2201/014 ,  B81C2201/0167 ,  H01F2007/068 ,  H01H50/005

Abstract: A method of fabricating an encapsulated micro electro-mechanical system (MEMS) and making of same that includes forming a dielectric layer, patterning an upper surface of the dielectric layer to form a trench, forming a release material within the trench, patterning an upper surface of the release material to form another trench, forming a first encapsulating layer that includes sidewalls within the another trench, forming a core layer within the first encapsulating layer, and forming a second encapsulating layer above the core layer, where the second encapsulating layer is connected to the sidewalls of the first encapsulating layer. Alternatively, the method includes forming a multilayer MEMS structure by photomasking processes to form a first metal layer, a second layer including a dielectric layer and a second metal layer, and a third metal layer. The core layer and the encapsulating layers are made of materials with complementary electrical, mechanical and/or magnetic properties.

Abstract translation: 一种制造封装的微电子机械系统（MEMS）的方法及其制造方法，包括形成电介质层，图案化介电层的上表面以形成沟槽，在沟槽内形成释放材料，图案化上表面 形成另一个沟槽，形成第一封装层，该第一封装层包括另一个沟槽内的侧壁，在第一封装层内形成核心层，以及在芯层上方形成第二封装层，其中第二封装层被连接 到第一封装层的侧壁。 或者，该方法包括通过光掩模工艺形成多层MEMS结构以形成第一金属层，第二层包括电介质层和第二金属层以及第三金属层。 芯层和封装层由具有互补的电，机械和/或磁性的材料制成。

公开(公告)号：US06489857B2

公开(公告)日：2002-12-03

申请号：US09727165

申请日：2000-11-30

Applicant: Kevin Petrarca ,  Robert A. Groves ,  Brian Herbst ,  Christopher Jahnes ,  Richard Volant

Inventor： Kevin Petrarca ,  Robert A. Groves ,  Brian Herbst ,  Christopher Jahnes ,  Richard Volant

IPC: H01P110

CPC classification number: H01H59/0009 ,  H01H2001/0084

Abstract: A micro electromechanical switch has a guidepost formed upon a substrate. A signal transmission line is formed on the substrate, with the signal transmission line having a gap and forming an open circuit. The switch further includes a switch body having a via opening formed therein, with the switch body being movably disposed along an length defined by the guide post. The guidepost is partially surrounded by the via opening.