-
1.发明授权Receiver-side adaptive equalization in source-synchronous chip-to-chip communication systems 有权源同步芯片到芯片通信系统中的接收机侧自适应均衡公开(公告)号：US07154972B2
公开(公告)日：2006-12-26
申请号：US10325542
申请日：2002-12-18
申请人： Aninda K. Roy , Claude R. Gauthier
发明人： Aninda K. Roy , Claude R. Gauthier
IPC分类号： H04B1/10
CPC分类号： H04L25/14
摘要： A communication system comprising transmitting circuitry arranged to transmit a data signal and a timing signal; and receiving circuitry arranged to receive the data signal and the timing signal. The receiving circuitry comprises a first finite impulse response filter arranged to generate a filtered timing signal dependent on the timing signal and a at least one mixer signal; a decision feedback circuit arranged to generate the at least one mixer signal dependent on the filtered timing signal and a calibration signal; and a second finite impulse response filter arranged to generate a filtered data signal dependent on the data signal and the at least one mixer signal.
摘要翻译： 一种通信系统，包括被布置为发送数据信号和定时信号的发送电路; 以及接收电路，被布置成接收数据信号和定时信号。 接收电路包括第一有限脉冲响应滤波器，其布置成根据定时信号和至少一个混频器信号产生经滤波的定时信号; 决定反馈电路，被配置为根据滤波的定时信号和校准信号产生至少一个混频器信号; 以及第二有限脉冲响应滤波器，其布置成根据所述数据信号和所述至少一个混频器信号产生经滤波的数据信号。
-
公开(公告)号：US07062688B2
公开(公告)日：2006-06-13
申请号：US10196384
申请日：2002-07-16
申请人： Claude R. Gauthier , Aninda K. Roy , Brian W. Amick , Dean Liu
发明人： Claude R. Gauthier , Aninda K. Roy , Brian W. Amick , Dean Liu
IPC分类号： G01R31/28
CPC分类号： G06F11/24
摘要： A technique for adjusting a communication system involves a link, where the link includes a data line arranged to transmit a data signal and a clock line adapted to transmit a clock signal. The technique uses one or more counters to test the transmission across the link. Dependent on one or more of these counters, a test circuit, connected to the link, compares a known test pattern signal to a latched test pattern signal transmitted on the data line. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal, where the adjustable clock signal determines when to latch the transmitted test pattern signal The test circuit adjusts a timing of the adjustable clock signal relative to the data signal of the link.
摘要翻译： 用于调整通信系统的技术涉及链路，其中链路包括被布置为发送数据信号的数据线和适于发送时钟信号的时钟线。 该技术使用一个或多个计数器来测试链路上的传输。 根据一个或多个这些计数器，连接到链路的测试电路将已知的测试模式信号与在数据线上发送的锁存的测试模式信号进行比较。 该测试电路包括调整电路，该调整电路被布置成从时钟信号产生可调节的时钟信号，其中可调节时钟信号确定何时锁存发送的测试图形信号。测试电路相对于数据信号的数据信号调整可调节时钟信号的定时 链接。
-
3.发明授权System, method and apparatus for improving sense amplifier performance characteristics using process feedback 有权使用过程反馈改善感测放大器性能特征的系统，方法和装置公开(公告)号：US06975144B2
公开(公告)日：2005-12-13
申请号：US10367340
申请日：2003-02-13
CPC分类号： G11C29/026 , G11C29/02 , G11C29/028 , G11C2029/5002 , H03K5/2481 , H03K2005/00123
摘要： A system and method of adjusting a sense amplifier to compensate for the process-type of the sense amplifier includes determining a process-type of the sense amplifier. An amplification control parameter is provided to the sense amplifier. The amplification control parameter is adjusted to adjust the sense amplifier according to the process-type of the sense amplifier.
摘要翻译： 调整读出放大器以补偿读出放大器的处理类型的系统和方法包括确定读出放大器的处理类型。 放大控制参数提供给读出放大器。 调整放大控制参数，以根据读出放大器的处理类型调整读出放大器。
-
公开(公告)号：US06781355B2
公开(公告)日：2004-08-24
申请号：US10274165
申请日：2002-10-18
IPC分类号： G05F1652
摘要： An apparatus for compensating for the effects of resonance in an integrated circuit's power distribution network is provided. A resonance detector monitors transmissions from the integrated circuit for certain bit patterns that may excite the power distribution network at a specific frequency and cause power supply resonance. Power supply resonance causes an increase in power supply impedance. When offending transmissions are detected, the resonance detector activates a damping element on the integrated circuit which dampens the resonance. The damping element is a resistive device between two power supply lines that decreases power supply impedance when activated.
摘要翻译： 提供了一种用于补偿集成电路配电网络中谐振的影响的装置。 谐振检测器监测来自集成电路的某些位模式的传输，其可以以特定频率激励配电网络并且引起电源谐振。 电源谐振导致电源阻抗增加。 当检测到异常传输时，谐振检测器激活集成电路上的阻尼谐振的阻尼元件。 阻尼元件是两个电源线之间的电阻设备，当电源被激活时，电阻阻抗会降低。
-
公开(公告)号：US07263628B2
公开(公告)日：2007-08-28
申请号：US10378295
申请日：2003-03-03
IPC分类号： H04L7/00
摘要： A Mobile Subscriber Directory Assistance (MSDA) system including originating carrier center initiating a directory assistance call, a directory assistance center providing a directory assistance service, and a search environment. The search environment includes an aggregated pointer database and at least one directory number resolution database. A caller requesting a telephone number is connected to a directory assistance service center where search criteria for the requested number are taken. The requested number is identified by searching the aggregated pointer database and the directory number resolution database. The caller is connected to the identified telephone number without releasing this identified telephone number.
摘要翻译： 方法和装置通过收发器电路来调整传播延迟。 发送装置被配置为产生控制信号，其中驱动电路的阻抗取决于控制信号。 偏置发生器可操作地连接到发送装置，并且取决于控制信号。 接收器电路可操作地连接到偏置发生器，其中偏置发生器布置成可操作地调节通过接收器电路的传播延迟。
-
公开(公告)号：US07110461B2
公开(公告)日：2006-09-19
申请号：US10198459
申请日：2002-07-18
IPC分类号： H04L27/00
CPC分类号： H04L25/03828 , H04L25/4906
摘要： A method and apparatus for enlarging data eyes in a wireline communication system involves pre-coding a data signal before transmission to generate a constant frequency characteristic independent of a state of the pre-coded data signal. The receiving circuit includes a circuit that temporally expands at least a portion of the pre-coded data signal. The portion of the temporally expanded data signal is latched by the receiving circuit.
摘要翻译： 用于在有线通信系统中放大数据眼睛的方法和装置包括在传输之前对数据信号进行预编码以产生与预编码数据信号的状态无关的恒定频率特性。 接收电路包括暂时扩展预编码数据信号的至少一部分的电路。 时间上扩展的数据信号的部分被接收电路锁存。
-
7.发明授权公开(公告)号：US07062662B2
公开(公告)日：2006-06-13
申请号：US10328069
申请日：2002-12-23
摘要： An apparatus for canceling an effect of power supply resonance is provided. The effect of power supply resonance is a variation in power supply voltage potential. This variation may substantially affect an output buffer by causing the output buffer's output to sag below desired values. A voltage regulating circuit is coupled to power supply lines local to the output buffer where the voltage regulating circuit is most effective in reducing voltage potential variation. An exemplary voltage regulating circuit is provided that uses charge-pumped capacitors to raise the power supply voltage potential when it falls below a desired value. A second example of a voltage regulating circuit uses charge-pumped capacitors to lower the power supply voltage potential when it rises above a desired value.
摘要翻译： 提供一种消除电源谐振效应的装置。 电源谐振的影响是电源电压电位的变化。 该变化可能通过使输出缓冲器的输出下降到期望值以下而基本上影响输出缓冲器。 电压调节电路耦合到输出缓冲器本地的电源线，其中电压调节电路在降低电压电位变化方面是最有效的。 提供了一种示例性的电压调节电路，其使用电荷泵电容器来降低电源电压下降到期望值以下的电压。 电压调节电路的第二示例使用电荷泵电容器，当其上升到期望值以上时降低电源电压电位。
-
公开(公告)号：US07043379B2
公开(公告)日：2006-05-09
申请号：US10277302
申请日：2002-10-22
IPC分类号： G06F19/00
CPC分类号： G01R31/31924 , G01R31/31932 , H04L1/242
摘要： A method for quantifying effects of resonance in an integrated circuit's power distribution network is provided. The power distribution network includes a first power supply line and a second power supply line to provide power to the integrated circuit. Test ranges are selected for two test parameters, reference voltage potential of a receiver and data transmission frequency of the integrated circuit. At each combination of the two test parameters, bit patterns are transmitted by the integrated circuit to the receiver. A comparison is made between the transmitted bits and the received bits to determine whether the transmitted bits were correctly received. The comparison may be used to determine and report a range of values for the reference voltage potential and data transmission frequency that allow the transmitted bits to be correctly received.
摘要翻译： 提供了一种用于量化集成电路配电网络中谐振效应的方法。 配电网络包括向集成电路提供电力的第一电源线和第二电源线。 选择两个测试参数的测试范围，接收机的参考电压电位和集成电路的数据传输频率。 在两个测试参数的每个组合中，位模式由集成电路传输到接收器。 在发送的比特和接收的比特之间进行比较，以确定发送的比特是否被正确地接收。 比较可以用于确定和报告允许正确接收发送位的参考电压电位和数据传输频率的值的范围。
-
9.发明授权Fully stable clock domain synchronization technique for input/output data transmission 有权完全稳定的时钟域同步技术，用于输入/输出数据传输公开(公告)号：US07376855B1
公开(公告)日：2008-05-20
申请号：US10849760
申请日：2004-05-20
申请人： Claude R. Gauthier , Aninda K. Roy
发明人： Claude R. Gauthier , Aninda K. Roy
CPC分类号： H04L7/10 , H04L7/0008 , H04L7/005 , H04L7/0083
摘要： Input/output data transmission between a transmitting integrated circuit and a receiving integrated circuit requires a clock domain synchronizer to synchronize incoming data aligned to a clock signal of the transmitting integrated circuit to a clock signal of the receiving integrated circuit. During a start-up routine, the clock domain synchronizer propagates a pre-determined pattern of data bits through a first circuit path designed to reduce or eliminate metastability. During a normal operations mode, the clock domain synchronizer synchronizes the data signal to the clock signal of the receiving integrated circuit through a second circuit path.
摘要翻译： 发送集成电路和接收集成电路之间的输入/输出数据传输需要时钟域同步器，以使与发送集成电路的时钟信号对准的输入数据与接收集成电路的时钟信号同步。 在启动程序期间，时钟域同步器通过设计用于减少或消除亚稳态的第一电路路径传播预定模式的数据位。 在正常操作模式期间，时钟域同步器通过第二电路路径将数据信号与接收集成电路的时钟信号同步。
-
公开(公告)号：US07369616B2
公开(公告)日：2008-05-06
申请号：US10373364
申请日：2003-02-24
申请人： Aninda K. Roy , Claude R. Gauthier
发明人： Aninda K. Roy , Claude R. Gauthier
IPC分类号： H04L27/00
CPC分类号： H04L5/06
摘要： The present invention is an apparatus and method for increasing the amount of data on a transmission path on a printed circuit board. Conventional methods allow only one data signal to be transmitted on the transmission path. The present invention uses multiple transmitters to modulate multiple data signals to form multiple modulated signals. The modulated signals are transmitted, possibly simultaneously, on the transmission path to receivers configured to demodulate individual modulated signals and recover the original data signals.
摘要翻译： 本发明是用于增加印刷电路板上的传输路径上的数据量的装置和方法。 传统方法仅允许在传输路径上传送一个数据信号。 本发明使用多个发射机来调制多个数据信号以形成多个调制信号。 调制信号可能同时在传输路径上被发送到被配置为解调各个调制信号并恢复原始数据信号的接收机。
-
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.021 秒)
