公开(公告)号：US06303513B1

公开(公告)日：2001-10-16

申请号：US09326334

申请日：1999-06-07

申请人： Anisul Khan ,  Ajay Kumar ,  Dragan V. Podlesnik ,  Jeffrey D. Chinn

发明人： Anisul Khan ,  Ajay Kumar ,  Dragan V. Podlesnik ,  Jeffrey D. Chinn

IPC分类号： H01L2100

CPC分类号： H01L21/67069 ,  H01J37/321 ,  H01J37/3299 ,  H01L21/3065

摘要： A method for controlling a profile of a structure formed on a substrate using nitrogen trifluoride (NF3) in a high density plasma (HDP) process. Changing the amount of NF3 in the plasma controls the profile of the structure. It has been found that the best results are obtained with an inductively coupled plasma wherein the ion density is at least 1012 ions/cm3. The method is particularly suited to etch processes such as deep trench etch in silicon wafers.

摘要翻译： 一种用于在高密度等离子体（HDP）工艺中使用三氟化氮（NF 3）在基板上形成的结构的轮廓进行控制的方法。 改变等离子体中NF3的量控制结构的轮廓。 已经发现，使用电感耦合等离子体获得最佳结果，其中离子密度为至少1012离子/ cm3。 该方法特别适用于蚀刻诸如硅晶片中的深沟槽蚀刻的工艺。

公开(公告)号：US06696365B2

公开(公告)日：2004-02-24

申请号：US10041540

申请日：2002-01-07

申请人： Ajay Kumar ,  Anisul Khan ,  Sanjay Thekdi ,  Dragan V. Podlesnik

发明人： Ajay Kumar ,  Anisul Khan ,  Sanjay Thekdi ,  Dragan V. Podlesnik

IPC分类号： H01L21302

CPC分类号： H01L21/3081 ,  H01L21/0276 ,  H01L21/3065 ,  H01L21/31116

摘要： A method of etching high aspect ratio, anisotropic deep trench openings in a silicon substrate coated with a multilayer mask comprising in sequence a pad oxide layer, a silicon nitride layer, a doped or undoped silicon oxide hard mask layer, a polysilicon hard mask layer, an antireflection coating and a patterned photoresist layer in a single chamber comprising patterning the antireflection coating and hard mask layer, removing the photoresist and antireflection layers with oxygen, using the patterned polysilicon as a hard mask layer etching an opening in the silicon oxide hard mask layer, the silicon nitride layer and the pad oxide layer, removing the polysilicon hard mask layer with CF4/CHF3, and etching an anisotropic deep trench in the silicon substrate using the patterned silicon oxide hard mask layer as a mask and an etchant mixture including nitrogen trifluoride that self-cleans the chamber.

摘要翻译： 一种在涂覆有多层掩模的硅衬底中蚀刻高纵横比的各向异性深沟槽开口的方法，其中依次包括衬垫氧化物层，氮化硅层，掺杂或未掺杂的氧化硅硬掩模层，多晶硅硬掩模层， 抗反射涂层和图案化的光致抗蚀剂层，其包括使抗反射涂层和硬掩模层图案化，用氧去除光致抗蚀剂和抗反射层，使用图案化多晶硅作为蚀刻氧化硅硬掩模层中的开口的硬掩模层 ，氮化硅层和焊盘氧化物层，用CF4 / CHF3去除多晶硅硬掩模层，并使用图案化的氧化硅硬掩模层作为掩模蚀刻硅衬底中的各向异性深沟槽，以及包括三氟化氮的蚀刻剂混合物 自我清理的房间。

公开(公告)号：US06642127B2

公开(公告)日：2003-11-04

申请号：US10035372

申请日：2001-10-19

申请人： Ajay Kumar ,  Padmapani C. Nallan ,  Anisul Khan ,  Dragan V. Podlesnik

发明人： Ajay Kumar ,  Padmapani C. Nallan ,  Anisul Khan ,  Dragan V. Podlesnik

IPC分类号： H01L21301

CPC分类号： H01L21/304 ,  H01L21/78

摘要： A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer. A well-known process is used to remove the adhesive material as well as any mask material and detach the dice from the carrier wafer.

摘要翻译： 一种使用等离子体蚀刻工艺对半导体晶片进行切割的方法和装置。 该方法开始于将图案化掩模应用于晶片上的集成电路。 模式涵盖电路并暴露骰子之间的街道。 接下来，该方法将均匀的粘合剂材料层沉积在载体晶片上。 要切割的晶片通过夹在要切割的晶片的底表面和载体晶片的顶表面之间的粘合剂材料固定到载体晶片上。 将要切割的载体晶片，粘合剂和晶片的组合组件放置在能够蚀刻硅的蚀刻反应器中。 当将反应性气体施加到组合组件时，蚀刻等离子体将消耗街道内的未受保护的硅，并将晶片切割成单独的集成电路芯片。 然后将载体晶片从蚀刻室移除，其中骰子仍附着到粘合剂层。 使用众所周知的方法去除粘合剂材料以及任何掩模材料，并将骰子从载体晶片上分离。

公开(公告)号：US5081002A

公开(公告)日：1992-01-14

申请号：US342528

申请日：1989-04-24

申请人： Mark N. Ruberto ,  Alan E. Willner ,  Richard M. Osgood, Jr. ,  Dragan V. Podlesnik

发明人： Mark N. Ruberto ,  Alan E. Willner ,  Richard M. Osgood, Jr. ,  Dragan V. Podlesnik

IPC分类号： H01L21/306

CPC分类号： H01L21/30612

摘要： The sensitivity of localized photochemical etching to the optical and electrical properties of multilayered semiconductor materials is utilized for selectively etching a laterally extending undercut in a buried layer. The semiconductor body is immersed in a suitable etching solution and a beam of light of appropriate wavelength and intensity is directed onto the semiconductor solution interface. The buried layer has a longer diffusion length for photogenerated carriers than the layers adjacent thereto, casuing carriers to diffuse away from the illuminated region within the buried layer and thereby etch the buried layer laterally, undercutting the adjacent layers.

摘要翻译： 局部光化学蚀刻对多层半导体材料的光学和电学性能的敏感性被用于选择性地蚀刻掩埋层中横向延伸的底切。 将半导体体浸入合适的蚀刻溶液中，将适当波长和强度的光束引导到半导体溶液界面上。 掩埋层对于光生载流子的扩散长度比与其相邻的层具有更长的扩散长度，引渡载体扩散远离掩埋层内的被照射区域，从而横向蚀刻掩埋层，从而切割相邻的层。