公开(公告)号：US06303513B1

公开(公告)日：2001-10-16

申请号：US09326334

申请日：1999-06-07

申请人： Anisul Khan ,  Ajay Kumar ,  Dragan V. Podlesnik ,  Jeffrey D. Chinn

发明人： Anisul Khan ,  Ajay Kumar ,  Dragan V. Podlesnik ,  Jeffrey D. Chinn

IPC分类号： H01L2100

CPC分类号： H01L21/67069 ,  H01J37/321 ,  H01J37/3299 ,  H01L21/3065

摘要： A method for controlling a profile of a structure formed on a substrate using nitrogen trifluoride (NF3) in a high density plasma (HDP) process. Changing the amount of NF3 in the plasma controls the profile of the structure. It has been found that the best results are obtained with an inductively coupled plasma wherein the ion density is at least 1012 ions/cm3. The method is particularly suited to etch processes such as deep trench etch in silicon wafers.

摘要翻译： 一种用于在高密度等离子体（HDP）工艺中使用三氟化氮（NF 3）在基板上形成的结构的轮廓进行控制的方法。 改变等离子体中NF3的量控制结构的轮廓。 已经发现，使用电感耦合等离子体获得最佳结果，其中离子密度为至少1012离子/ cm3。 该方法特别适用于蚀刻诸如硅晶片中的深沟槽蚀刻的工艺。

公开(公告)号：US06696365B2

公开(公告)日：2004-02-24

申请号：US10041540

申请日：2002-01-07

申请人： Ajay Kumar ,  Anisul Khan ,  Sanjay Thekdi ,  Dragan V. Podlesnik

发明人： Ajay Kumar ,  Anisul Khan ,  Sanjay Thekdi ,  Dragan V. Podlesnik

IPC分类号： H01L21302

CPC分类号： H01L21/3081 ,  H01L21/0276 ,  H01L21/3065 ,  H01L21/31116

摘要： A method of etching high aspect ratio, anisotropic deep trench openings in a silicon substrate coated with a multilayer mask comprising in sequence a pad oxide layer, a silicon nitride layer, a doped or undoped silicon oxide hard mask layer, a polysilicon hard mask layer, an antireflection coating and a patterned photoresist layer in a single chamber comprising patterning the antireflection coating and hard mask layer, removing the photoresist and antireflection layers with oxygen, using the patterned polysilicon as a hard mask layer etching an opening in the silicon oxide hard mask layer, the silicon nitride layer and the pad oxide layer, removing the polysilicon hard mask layer with CF4/CHF3, and etching an anisotropic deep trench in the silicon substrate using the patterned silicon oxide hard mask layer as a mask and an etchant mixture including nitrogen trifluoride that self-cleans the chamber.

摘要翻译： 一种在涂覆有多层掩模的硅衬底中蚀刻高纵横比的各向异性深沟槽开口的方法，其中依次包括衬垫氧化物层，氮化硅层，掺杂或未掺杂的氧化硅硬掩模层，多晶硅硬掩模层， 抗反射涂层和图案化的光致抗蚀剂层，其包括使抗反射涂层和硬掩模层图案化，用氧去除光致抗蚀剂和抗反射层，使用图案化多晶硅作为蚀刻氧化硅硬掩模层中的开口的硬掩模层 ，氮化硅层和焊盘氧化物层，用CF4 / CHF3去除多晶硅硬掩模层，并使用图案化的氧化硅硬掩模层作为掩模蚀刻硅衬底中的各向异性深沟槽，以及包括三氟化氮的蚀刻剂混合物 自我清理的房间。

公开(公告)号：US06471833B2

公开(公告)日：2002-10-29

申请号：US09853847

申请日：2001-05-11

申请人： Ajay Kumar ,  Anisul Khan ,  Jeffrey D Chin ,  Dragan V Podlesnik

发明人： Ajay Kumar ,  Anisul Khan ,  Jeffrey D Chin ,  Dragan V Podlesnik

IPC分类号： C23C1434

CPC分类号： H01L21/67069 ,  H01J37/321 ,  H01J37/32935 ,  H01L21/3065

摘要： This invention is directed to a method for rapid plasma etching of materials which are difficult to etch at a high rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes the use of a plasma source gas that includes an etchant gas and a sputtering gas. Two separate power sources are used in the etching process and the power to each power source as well as the ratio between the flow rates of the etchant gas and sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched. In the second step, a low etch rate process having an etch rate below about two microns per minute is used to remove any residual material not removed by the first etch step.

摘要翻译： 本发明涉及用于快速等离子体蚀刻难以高速蚀刻的材料的方法。 该方法在等离子体蚀刻中超过5微米厚的氮化硅层特别有用。 该方法包括使用包括蚀刻剂气体和溅射气体的等离子体源气体。 在蚀刻工艺中使用两个单独的电源，并且可以有利地调整蚀刻剂气体和溅射气体的流量之间的比例，以获得大于每分钟2微米的氮化硅的蚀刻速率 。 另外，本发明的方法的一个实施例提供了两个蚀刻步骤方法，其将高蚀刻速率工艺与低蚀刻速率工艺组合以实现高通量，同时最小化对下层的损伤的可能性。 两步法的第一蚀刻步骤提供了每分钟约2微米的高蚀刻速率，以便基本上除去所有待蚀刻的层。 在第二步骤中，使用蚀刻速率低于每分钟约2微米的低蚀刻速率工艺来去除通过第一蚀刻步骤未被去除的任何残留材料。

公开(公告)号：US06642127B2

公开(公告)日：2003-11-04

申请号：US10035372

申请日：2001-10-19

申请人： Ajay Kumar ,  Padmapani C. Nallan ,  Anisul Khan ,  Dragan V. Podlesnik

发明人： Ajay Kumar ,  Padmapani C. Nallan ,  Anisul Khan ,  Dragan V. Podlesnik

IPC分类号： H01L21301

CPC分类号： H01L21/304 ,  H01L21/78

摘要： A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer. A well-known process is used to remove the adhesive material as well as any mask material and detach the dice from the carrier wafer.

摘要翻译： 一种使用等离子体蚀刻工艺对半导体晶片进行切割的方法和装置。 该方法开始于将图案化掩模应用于晶片上的集成电路。 模式涵盖电路并暴露骰子之间的街道。 接下来，该方法将均匀的粘合剂材料层沉积在载体晶片上。 要切割的晶片通过夹在要切割的晶片的底表面和载体晶片的顶表面之间的粘合剂材料固定到载体晶片上。 将要切割的载体晶片，粘合剂和晶片的组合组件放置在能够蚀刻硅的蚀刻反应器中。 当将反应性气体施加到组合组件时，蚀刻等离子体将消耗街道内的未受保护的硅，并将晶片切割成单独的集成电路芯片。 然后将载体晶片从蚀刻室移除，其中骰子仍附着到粘合剂层。 使用众所周知的方法去除粘合剂材料以及任何掩模材料，并将骰子从载体晶片上分离。

公开(公告)号：US06270634B1

公开(公告)日：2001-08-07

申请号：US09430798

申请日：1999-10-29

申请人： Ajay Kumar ,  Anisul Khan ,  Jeffrey D Chinn ,  Dragan Podlesnik

发明人： Ajay Kumar ,  Anisul Khan ,  Jeffrey D Chinn ,  Dragan Podlesnik

IPC分类号： C23C1434

CPC分类号： H01L21/67069 ,  H01J37/321 ,  H01J37/32935 ,  H01L21/3065

摘要： This invention is directed to a method for rapid plasma etching of materials which are difficult to etch at a high rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes the use of a plasma source gas that includes an etchant gas and a sputtering gas. Two separate power sources are used in the etching process and the power to each power source as well as the ratio between the flow rates of the etchant gas and sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched. In the second step, a low etch rate process having an etch rate below about two microns per minute is used to remove any residual material not removed by the first etch step.

摘要翻译： 本发明涉及用于快速等离子体蚀刻难以高速蚀刻的材料的方法。 该方法在等离子体蚀刻中超过5微米厚的氮化硅层特别有用。 该方法包括使用包括蚀刻剂气体和溅射气体的等离子体源气体。 在蚀刻工艺中使用两个单独的电源，并且可以有利地调整蚀刻剂气体和溅射气体的流量之间的比例，以获得大于每分钟2微米的氮化硅的蚀刻速率 。 另外，本发明的方法的一个实施例提供了两个蚀刻步骤方法，其将高蚀刻速率工艺与低蚀刻速率工艺组合以实现高通量，同时最小化对下层的损伤的可能性。 两步法的第一蚀刻步骤提供了每分钟约2微米的高蚀刻速率，以便基本上除去所有待蚀刻的层。 在第二步骤中，使用蚀刻速率低于每分钟约2微米的低蚀刻速率工艺来去除通过第一蚀刻步骤未被去除的任何残留材料。

公开(公告)号：US06372655B2

公开(公告)日：2002-04-16

申请号：US09836934

申请日：2001-04-17

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

公开(公告)号：US06518192B2

公开(公告)日：2003-02-11

申请号：US10013115

申请日：2001-12-07

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.

公开(公告)号：US06391788B1

公开(公告)日：2002-05-21

申请号：US09513552

申请日：2000-02-25

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L2100

CPC分类号： H01L21/30655 ,  B81B2203/033 ,  B81C1/00571 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/32137

摘要： A two etchant etch method for etching a layer that is part of a masked structure is described. The method is useful, for example, in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used advantageously to optimize a plasma etch process capable of etching strict profile control trenches with 89°+/−1° sidewalls in silicon layers formed as part of a mask structure where the mask structure induces variations in etch rate. The inventive two etchant etch method etches a layer in a structure with a first etchant etch until a layer in a fastest etching region is etched. The layer is then etched with a second etchant until a layer in a region with a slowest etch rate is etched. A second etchant may also be selected to provide sidewall passivation and selectivity to an underlying layer of the structure.

摘要翻译： 描述了用于蚀刻作为掩模结构的一部分的层的两种蚀刻剂蚀刻方法。 该方法例如在微电机械系统（MEMS）应用中以及集成电路和其它电子设备的制造中是有用的。 该方法可以有利地用于优化等离子体蚀刻工艺，该等离子体蚀刻工艺能够蚀刻具有89°+/- 1°侧壁的严格轮廓控制沟槽，该硅层形成为掩模结构的一部分，其中掩模结构引起蚀刻速率的变化。 本发明的两种蚀刻剂蚀刻方法蚀刻具有第一蚀刻剂蚀刻的结构中的层，直到蚀刻最快蚀刻区域中的层。 然后用第二蚀刻剂蚀刻该层，直到蚀刻具有最慢蚀刻速率的区域中的层。 还可以选择第二蚀刻剂以向结构的下层提供侧壁钝化和选择性。

公开(公告)号：US06802933B2

公开(公告)日：2004-10-12

申请号：US09740146

申请日：2000-12-18

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： C23F100

CPC分类号： H01L21/67069 ,  H01L21/3065 ,  H01L21/76232 ,  H01L27/1087 ,  Y10S156/916

摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.

摘要翻译： 本发明涉及一种用于蚀刻半导体衬底上的薄膜和清洗蚀刻室的方法。 该方法包括改进的处理顺序和清洁方法，其中通过用于从本基板去除暴露的材料层的蚀刻工艺来清洁由先前基板处理形成的残留物。 该方法通过将该步骤与在本发明的基底上进行的蚀刻步骤清洗来自先前基底的残余物来提供改进的基底产量。 申请人已经发现该方法在诸如DRAM堆叠的处理结构中特别有用，特别是在通过在先前硅衬底中蚀刻的沟槽形成残留物的情况下，并且从本衬底蚀刻的暴露层是氮化硅。

公开(公告)号：US06318384B1

公开(公告)日：2001-11-20

申请号：US09405349

申请日：1999-09-24

申请人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

发明人： Anisul Khan ,  Ajay Kumar ,  Jeffrey D. Chinn ,  Dragan Podlesnik

IPC分类号： H01L21302

CPC分类号： H01L21/67069 ,  H01L21/3065 ,  H01L21/76232 ,  H01L27/1087 ,  Y10S156/916

摘要： This invention is directed to a method for etching films on semiconductor substrates and cleaning etch chambers. The method includes an improved processing sequence and cleaning method where residue formed from processing a previous substrate are cleaned by the etching process used to remove an exposed layer of material from the present substrate. The process provides improved substrate throughput by combining the step to clean residue from a previous substrate with an etch step conducted on the present substrate. Applicants have found the method particularly useful in processing structures such as DRAM stacks, especially where the residue is formed by a trench etched in the previous silicon substrate and the exposed layer etched from the present substrate is silicon nitride.

摘要翻译： 本发明涉及一种用于蚀刻半导体衬底上的薄膜和清洗蚀刻室的方法。 该方法包括改进的处理顺序和清洁方法，其中通过用于从本基板去除暴露的材料层的蚀刻工艺来清洁由先前基板处理形成的残留物。 该方法通过将该步骤与在本发明的基底上进行的蚀刻步骤清洗来自先前基底的残余物来提供改进的基底产量。 申请人已经发现该方法在诸如DRAM堆叠的处理结构中特别有用，特别是在通过在先前硅衬底中蚀刻的沟槽形成残留物的情况下，并且从本衬底蚀刻的暴露层是氮化硅。