公开(公告)号：US20070200744A1

公开(公告)日：2007-08-30

申请号：US11276451

申请日：2006-02-28

申请人： Anthony Bonaccio ,  Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone ,  Stephen Wyatt

发明人： Anthony Bonaccio ,  Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone ,  Stephen Wyatt

IPC分类号： H03M1/66

CPC分类号： G05F1/46

摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.

摘要翻译： 用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。 模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。 控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

公开(公告)号：US20070075789A1

公开(公告)日：2007-04-05

申请号：US11163013

申请日：2005-09-30

申请人： Anthony Bonaccio ,  Hayden Cranford ,  Joseph Iadanza ,  Stephen Wyatt

发明人： Anthony Bonaccio ,  Hayden Cranford ,  Joseph Iadanza ,  Stephen Wyatt

IPC分类号： H03B5/12

CPC分类号： H03L7/093 ,  H03L7/0891

摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.

摘要翻译： 提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。 根据本发明的实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组 电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。

公开(公告)号：US20070075731A1

公开(公告)日：2007-04-05

申请号：US11163015

申请日：2005-09-30

申请人： Igor Arsovski ,  Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

发明人： Igor Arsovski ,  Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

IPC分类号： H03K19/003

CPC分类号： H03K19/00346

摘要： An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.

摘要翻译： 集成电路设备包括功能逻辑，抗噪声机器和状态监测点，其为抗噪声机器提供与用于监视功能逻辑状态的功能逻辑的接口。 抗噪声机器包括定义用于功能逻辑的噪声前导状态的标记，以及耦合到状态监测点的识别逻辑。 抗噪声机器可操作以响应于与标记匹配的功能逻辑噪声前导状态中的识别逻辑检测产生抗噪声。

公开(公告)号：US20060181323A1

公开(公告)日：2006-08-17

申请号：US10906343

申请日：2005-02-15

申请人： Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

发明人： Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00032

摘要： A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.

摘要翻译： 在集成电路的模拟域和数字域之间平衡信号互连路径延迟的方法包括将测试信号应用于模拟域和数字域之间的多个通信路径中的所选择的一个。 通过调整配置在所选择的通信路径内的延迟元件的体偏置电压来平衡测试信号的上升沿延迟和下降沿延迟。 将每个剩余通信路径的上升沿延迟和下降沿延迟与所选择的通信路径的均衡的上升沿延迟和下降沿延迟进行比较，并且配置多个延迟元件中的一个或多个的体偏置电压 在每个剩余的通信路径内进行调整，直到相应的上升沿和下降沿延迟与所选通信路径的均衡上升沿延迟和下降沿延迟相匹配。

公开(公告)号：US20050108667A1

公开(公告)日：2005-05-19

申请号：US10707068

申请日：2003-11-19

申请人： Joseph Iadanza ,  Raminderpal Singh ,  Sebastian Ventrone ,  Ivan Wemple

发明人： Joseph Iadanza ,  Raminderpal Singh ,  Sebastian Ventrone ,  Ivan Wemple

IPC分类号： G06F17/50 ,  G06G7/62

CPC分类号： G06F17/5045

摘要： A method for designing an integrated circuit having multiple voltage domains, including: (a) generating a logical integrated circuit design from information contained in a high-level design file, the high-level design file defining global connection declarations and voltage domain connection declarations; (b) synthesizing the logical integrated circuit design into a synthesized integrated circuit design based upon the logical integrated circuit design, information in a preferred components file and information in a voltage domain definition file; (c) generating a noise model from the synthesized integrated circuit design based on information in the voltage domain definition file and a design constraint file; and (d) simulating the noise model against constraints in the design constraint file and constraints in a circuit level profile file to determine if the synthesized integrated circuit design meets predetermined noise simulation targets.

摘要翻译： 一种用于设计具有多个电压域的集成电路的方法，包括：（a）从包含在高级设计文件中的信息，定义全局连接声明和电压域连接声明的高级设计文件生成逻辑集成电路设计; （b）基于逻辑集成电路设计，优选组件文件中的信息和电压域定义文件中的信息，将逻辑集成电路设计合成为合成集成电路设计; （c）基于电压域定义文件和设计约束文件中的信息从合成的集成电路设计中产生噪声模型; 和（d）根据设计约束文件中的约束和电路级配置文件中的约束模拟噪声模型，以确定合成的集成电路设计是否满足预定的噪声模拟目标。

公开(公告)号：US20070220468A1

公开(公告)日：2007-09-20

申请号：US11752035

申请日：2007-05-22

申请人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

发明人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

公开(公告)号：US20060101362A1

公开(公告)日：2006-05-11

申请号：US10904397

申请日：2004-11-08

申请人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

发明人： Allen Haar ,  Joseph Iadanza ,  Sebastian Ventrone ,  Ivan Wemple

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： A method for converting globally clock-gated circuits to locally clock-gated circuits is disclosed. A timing analysis is initially performed on an integrated circuit (IC) design to generate a slack time report for all globally clock-gated circuits within the IC design. Based on their respective slack time indicated in the slack time report, all globally clock-gated circuits that should be connected to locally generated clocks are identified. After disconnecting from a global clock tree, each of the identified globally clock-gated circuits is subsequently connected to a locally generated clock having a clock delay comparable to its slack time indicated in the slack time report.

摘要翻译： 公开了一种将全局时钟选通电路转换为本地时钟门控电路的方法。 最初在集成电路（IC）设计上执行时序分析，以便为IC设计中的所有全局时钟门控电路生成松弛时间报告。 根据松弛时间报告中指定的各自的松弛时间，可以识别应连接到本地生成的时钟的所有全局时钟选通电路。 在与全局时钟树断开连接之后，所识别的全局时钟门控电路中的每一个随后连接到具有与其在松弛时间报告中指示的松弛时间相当的时钟延迟的本地产生的时钟。

公开(公告)号：US20070115019A1

公开(公告)日：2007-05-24

申请号：US11164040

申请日：2005-11-08

申请人： Anthony Bonaccio ,  Allen Haar ,  Joseph Iadanza ,  Douglas Stout ,  Ivan Wemple

发明人： Anthony Bonaccio ,  Allen Haar ,  Joseph Iadanza ,  Douglas Stout ,  Ivan Wemple

IPC分类号： G01R31/26

CPC分类号： G01R31/2884 ,  G01R35/005

摘要： A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.

摘要翻译： 公开了一种用于改变电路特性以使它们与集成电路内的器件的处理参数无关的方法。 通过在晶片上的选择性芯片组上的切口或片上内置测试来测量工艺参数，并将结果存储在每个相应芯片内的存储装置上。 然后，对于剩余的每个芯片，执行二维内插，以基于测量值确定各个芯片的处理参数值。 内插值与芯片在efuse控制文件中的坐标一起被记录。 这样的信息随后被存储在芯片内的efuse模块中。 片上数字控制结构用于根据存储在efuse模块中的信息来调整芯片内的功能组件的某些操作特性。

公开(公告)号：US20050204318A1

公开(公告)日：2005-09-15

申请号：US10708608

申请日：2004-03-15

申请人： Joseph Iadanza ,  Raminderpal Singh

发明人： Joseph Iadanza ,  Raminderpal Singh

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5081

摘要： A method of analyzing and designing circuits comprising creating a set of interpolated models for transistor devices; creating a set of characterized (direct fit) models for the transistor devices; analyzing the transistor devices within a netlist for matches in the set of characterized models; and providing a choice of using the matched characterized models or one of the interpolated models in designing the circuits. The method further comprises schematically simulating a custom circuit; back annotating to a schematic circuit which of the transistors use direct-fit models and which of the transistor devices are interpolated; determining whether the transistor devices are in any of cutoff, saturation, static linear, and dynamic linear mode during simulation of the custom circuit; removing the saturation and dynamic linear mode transistor devices; back annotating the netlist to a schematic with a predetermined device state; and performing sensitivity analysis on saturation and dynamic linear mode transistor devices.

摘要翻译： 一种分析和设计电路的方法，包括为晶体管器件创建一组内插模型; 为晶体管器件创建一组特征（直接拟合）模型; 分析网表中的晶体管器件，用于在该特征模型集合中进行匹配; 并提供在设计电路中使用匹配的特征模型或内插模型之一的选择。 该方法还包括示意性地模拟定制电路; 反向注释到晶体管中的哪一个使用直接拟合模型和晶体管器件中的哪些被内插的原理图电路; 在定制电路的仿真期间确定晶体管器件是否处于截止，饱和，静态线性和动态线性模式中的任何一种; 去除饱和和动态线性模式晶体管器件; 将网表注释到具有预定设备状态的原理图; 并对饱和和动态线性模式晶体管器件执行灵敏度分析。

公开(公告)号：US20070278582A1

公开(公告)日：2007-12-06

申请号：US11841247

申请日：2007-08-20

申请人： Kenneth Goodnow ,  Joseph Iadanza ,  Edward Nowak ,  Douglas Stout

发明人： Kenneth Goodnow ,  Joseph Iadanza ,  Edward Nowak ,  Douglas Stout

IPC分类号： H01L29/739

CPC分类号： H01L29/42384 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78648

摘要： A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.