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20 条记录 (耗时 0.018 秒)

    STRUCTURE AND METHOD FOR PROVIDING GATE LEAKAGE ISOLATION LOCALLY WITHIN ANALOG CIRCUITS
    1.
    发明申请
    STRUCTURE AND METHOD FOR PROVIDING GATE LEAKAGE ISOLATION LOCALLY WITHIN ANALOG CIRCUITS 失效
    在模拟电路中局部地提供闸门泄漏隔离的结构和方法

    公开(公告)号：US20070075789A1

    公开(公告)日：2007-04-05

    申请号：US11163013

    申请日：2005-09-30

    申请人： Anthony Bonaccio ,  Hayden Cranford ,  Joseph Iadanza ,  Stephen Wyatt

    发明人： Anthony Bonaccio ,  Hayden Cranford ,  Joseph Iadanza ,  Stephen Wyatt

    IPC分类号： H03B5/12

    CPC分类号： H03L7/093 ,  H03L7/0891

    摘要： A loop filter for a phase-locked-loop is provided, comprising a set of capacitor banks coupled in parallel to form the loop filter, and a detection circuit for identifying and isolating defective capacitor banks. A method for providing a loop filter for a phase-locked-loop in accordance with an embodiment of the present invention includes the steps of forming the loop filter using a set of capacitor banks coupled in parallel, detecting any defective capacitor banks in the set of capacitor banks, isolating each defective capacitor bank, providing a set of redundant capacitor banks, and replacing each defective capacitor bank with a redundant capacitor bank from the set of redundant capacitor banks.

    摘要翻译： 提供了一种用于锁相环的环路滤波器，包括并联耦合以形成环路滤波器的一组电容器组，以及用于识别和隔离有缺陷的电容器组的检测电路。 根据本发明的实施例的用于提供用于锁相环的环路滤波器的方法包括以下步骤：使用并联耦合的一组电容器组形成环路滤波器，检测该组中的任何有缺陷的电容器组 电容器组，隔离每个有缺陷的电容器组，提供一组冗余电容器组，并从冗余电容器组组中的冗余电容器组替换每个有缺陷的电容器组。

    BODY-BIASED ENHANCED PRECISION CURRENT MIRROR
    3.
    发明申请
    BODY-BIASED ENHANCED PRECISION CURRENT MIRROR 失效
    身体偏心增强精度电流镜

    公开(公告)号：US20060192611A1

    公开(公告)日：2006-08-31

    申请号：US10906628

    申请日：2005-02-28

    申请人： Anthony Bonaccio ,  Hayden Cranford

    发明人： Anthony Bonaccio ,  Hayden Cranford

    IPC分类号： G05F1/10

    CPC分类号： G05F3/262

    摘要： A body-biased enhanced current mirror reference circuit is disclosed wherein the body bias voltage of a current mirror device is varied to adjust its threshold voltage. Both the drain and body potentials of a replica mirror transistor are controlled to selected values. The drain is set to an expected DC voltage output of an NFET current mirror device. The body potential is set to a maximum desired value to prevent forward biasing of the body-to-diffusion junction(s) of one or more current mirror devices, which is accomplished by a feedback control circuit. A low-frequency, low-precision op amp drives the gate of a replica load device so that the body of the replica NFET current mirror device is set to a maximum bias voltage. The maximum bias voltage is also used to bias the body of a diode connected NMOS reference transistor, so that the current in the NFET current mirror device will be approximately equal to the current in the diode-connected NMOS reference. An auxiliary NFET current mirror device may be added to the body-biased enhanced current mirror circuit with the body connected to ground as in the unmodified current mirror to negate a non-monotonicity of the current output.

    摘要翻译： 公开了一种体偏置增强电流镜参考电路，其中电流镜装置的体偏置电压被改变以调节其阈值电压。 复制镜晶体管的漏极和体电位都被控制为选定值。 漏极设置为NFET电流镜器件的预期直流电压输出。 身体电位被设置为最大期望值，以防止由反馈控制电路实现的一个或多个电流镜装置的体对扩散结的正向偏置。 低频，低精度运算放大器驱动复制负载装置的栅极，使得复制NFET电流镜装置的主体被设置为最大偏置电压。 最大偏置电压也用于偏置二极管连接的NMOS参考晶体管的主体，使得NFET电流镜器件中的电流将近似等于连接二极管的NMOS参考电流。 辅助NFET电流镜装置可以被添加到主体偏置的增强电流镜电路中，其中主体连接到地面，如在未修改的电流镜中，以消除电流输出的非单调性。

    METHOD AND APPARATUS FOR STORING CIRCUIT CALIBRATION INFORMATION
    5.
    发明申请
    METHOD AND APPARATUS FOR STORING CIRCUIT CALIBRATION INFORMATION 失效
    存储电路校准信息的方法和装置

    公开(公告)号：US20070115019A1

    公开(公告)日：2007-05-24

    申请号：US11164040

    申请日：2005-11-08

    申请人： Anthony Bonaccio ,  Allen Haar ,  Joseph Iadanza ,  Douglas Stout ,  Ivan Wemple

    发明人： Anthony Bonaccio ,  Allen Haar ,  Joseph Iadanza ,  Douglas Stout ,  Ivan Wemple

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2884 ,  G01R35/005

    摘要： A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.

    摘要翻译： 公开了一种用于改变电路特性以使它们与集成电路内的器件的处理参数无关的方法。 通过在晶片上的选择性芯片组上的切口或片上内置测试来测量工艺参数，并将结果存储在每个相应芯片内的存储装置上。 然后，对于剩余的每个芯片，执行二维内插，以基于测量值确定各个芯片的处理参数值。 内插值与芯片在efuse控制文件中的坐标一起被记录。 这样的信息随后被存储在芯片内的efuse模块中。 片上数字控制结构用于根据存储在efuse模块中的信息来调整芯片内的功能组件的某些操作特性。

    Damping of LC Ringing in IC (Integrated Circuit) Power Distribution Systems
    6.
    发明申请
    Damping of LC Ringing in IC (Integrated Circuit) Power Distribution Systems 失效
    IC（集成电路）配电系统中LC振荡的阻尼

    公开(公告)号：US20050110551A1

    公开(公告)日：2005-05-26

    申请号：US10707171

    申请日：2003-11-25

    申请人： Anthony Bonaccio ,  Allen Haar ,  Michael Sorna ,  Ivan Wemple ,  Stephen Wyatt

    发明人： Anthony Bonaccio ,  Allen Haar ,  Michael Sorna ,  Ivan Wemple ,  Stephen Wyatt

    IPC分类号： G05F1/10 ,  G05F3/02 ,  H03K17/16 ,  H03L5/00

    CPC分类号： G11C5/14 ,  H01L23/50 ,  H01L2924/0002 ,  H03K17/164 ,  H01L2924/00

    摘要： A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.

    摘要翻译： 用于阻尼集成电路（IC）配电系统中LC（电感 - 电容）振铃的结构和方法。 该结构包括与多个电开关并联电连接的电阻。 电阻和电气开关与封装和片上配电电路串联电连接。 当片上切换活动产生IC功率需求的突然和明显的变化时，电开关被打开以临时增加与电源串联的电阻。 这用于抑制功率分配LC振铃。 之后，电开关闭合以分流串联电阻并降低电源结构中稳态电压降的水平。

    ADJUSTABLE PHASE CONTROLLED CLOCK AND DATA RECOVERY CIRCUIT
    8.
    发明申请
    ADJUSTABLE PHASE CONTROLLED CLOCK AND DATA RECOVERY CIRCUIT 失效
    可调相位控制时钟和数据恢复电路

    公开(公告)号：US20070222488A1

    公开(公告)日：2007-09-27

    申请号：US11757510

    申请日：2007-06-04

    申请人： Anthony Bonaccio ,  Charles Masenas ,  Troy Seman

    发明人： Anthony Bonaccio ,  Charles Masenas ,  Troy Seman

    IPC分类号： H03L7/00

    CPC分类号： H03L7/081 ,  H04L7/033

    摘要： A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.

    摘要翻译： 一种时钟和数据恢复电路，包括：用于产生第一和第二时钟信号的装置; 用于接收第一时钟信号并用于从第一时钟信号产生第三时钟信号的装置，以及用于接收第二时钟信号并产生第四时钟信号的装置，其中第三和第四时钟信号中的至少一个在相位上是不同的 分别从第一和第二时钟信号; 用于接收第三和第四时钟信号和串行数据流并用于产生重建的串行数据流和相位误差信号的装置; 用于接收相位误差信号并产生相位调整信号的装置，以及用于在反馈回路中由时钟产生电路接收相位调整信号的装置，以调整第一和第二时钟信号的相位。

    Programmable capacitors and methods of using the same
    9.
    发明申请
    Programmable capacitors and methods of using the same 有权
    可编程电容器及其使用方法

    公开(公告)号：US20070188249A1

    公开(公告)日：2007-08-16

    申请号：US11353516

    申请日：2006-02-14

    申请人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

    发明人： Wagdi Abadeer ,  Anthony Bonaccio ,  Jack Mandelman ,  William Tonti ,  Sebastian Ventrone

    IPC分类号： H03B5/12

    CPC分类号： H03L7/099 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03L7/095 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

    摘要： In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种调整半导体器件的电容的方法。 第一种方法包括以下步骤：（1）提供包括具有约3.9至约25的介电常数的介电材料的晶体管，其中该晶体管适于在第一模式下工作以提供电容，并进一步适于在 将晶体管的阈值电压从初始阈值电压改变到改变的阈值电压，使得当在第一模式中操作时，改变的阈值电压影响由晶体管提供的电容; 和（2）在电路中采用晶体管。 提供了许多其他方面。