公开(公告)号：US5835502A

公开(公告)日：1998-11-10

申请号：US673258

申请日：1996-06-28

申请人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Leland Leslie Day ,  Paul Allen Ganfield ,  Murali Vaddigiri ,  Paul Wong

发明人： Anthony Gus Aipperspach ,  Todd Alan Christensen ,  Leland Leslie Day ,  Paul Allen Ganfield ,  Murali Vaddigiri ,  Paul Wong

IPC分类号： G06F12/16 ,  G06F11/22 ,  G11C29/02 ,  G11C29/12 ,  G11C29/32 ,  G06F11/00

CPC分类号： G11C29/32

摘要： A method and apparatus for handling variable data word widths and array depths in an array built-in self-test system for testing a plurality of memory arrays using a single controller. Each array includes a predetermined row and column address depth and data word width. Each array further includes a scan register. A universal test data word is generated and sent to the scan register of each array. The universal length test data word has a length dependent upon the maximum row address depth, maximum column address depth and/or the maximum data word width. A portion of the test data word which exceeds the column address depth, row address depth and/or the data word width of a particular array is shifted off the end of the scan register of the particular array.

摘要翻译： 一种用于处理阵列内置自检系统中的可变数据字宽度和阵列深度的方法和装置，用于使用单个控制器来测试多个存储器阵列。 每个阵列包括预定的行和列地址深度和数据字宽度。 每个阵列还包括扫描寄存器。 生成通用测试数据字并将其发送到每个阵列的扫描寄存器。 通用长度测试数据字的长度取决于最大行地址深度，最大列地址深度和/或最大数据字宽度。 超过特定阵列的列地址深度，行地址深度和/或数据字宽度的测试数据字的一部分从特定阵列的扫描寄存器的结尾偏移。

公开(公告)号：US06260164B1

公开(公告)日：2001-07-10

申请号：US09127355

申请日：1998-07-31

申请人： Anthony Gus Aipperspach ,  Leland Leslie Day ,  Paul Allen Ganfield ,  Charles Luther Johnson

发明人： Anthony Gus Aipperspach ,  Leland Leslie Day ,  Paul Allen Ganfield ,  Charles Luther Johnson

IPC分类号： G01R3128

CPC分类号： G11C11/417

摘要： A functional unit, such as an SRAM, in a single clock chip design that contains a scan path can be clocked on either rising edge and falling edge of the clock. The functional unit includes a clock signal having two phases and a plurality of latches for scanning. Two scan latches are added outside the array of the functional unit. In one clock phase, the two scan latches form a latch pair which is connected to the array at Scan-in side. In the other clock phase, one scan latch is connected to the array at the Scan-in side, and the other scan latch is connected to the array at the Scan-out side. In scan/hold operations, a first control signal for the array which is clocked at the falling edge of the clock leads a second control signal for the array which is clocked at the rising edge of the clock. In ABIST/functional operations, the first control signal for the array which is clocked at the falling edge of the clock trails the second control signal for the array which is clocked at the rising edge of the clock.

摘要翻译： 包含扫描路径的单个时钟芯片设计中的诸如SRAM的功能单元可以在时钟的上升沿和下降沿被计时。 功能单元包括具有两相的时钟信号和用于扫描的多个锁存器。 两个扫描锁存器被添加到功能单元的阵列之外。 在一个时钟相位中，两个扫描锁存器形成一个锁存器对，其在Scan-in侧连接到阵列。 在另一个时钟阶段，一个扫描锁存器连接到Scan-in侧的阵列，另一个扫描锁存器连接到Scan-out侧的阵列。 在扫描/保持操作中，在时钟的下降沿被计时的阵列的第一控制信号引出在时钟的上升沿被计时的阵列的第二控制信号。 在ABIST /功能操作中，在时钟下降沿时钟脉冲的阵列的第一个控制信号跟踪在时钟上升沿时钟脉冲的阵列的第二个控制信号。

公开(公告)号：US5663966A

公开(公告)日：1997-09-02

申请号：US686105

申请日：1996-07-24

申请人： Leland Leslie Day ,  Steven Michael Douskey ,  Paul Allen Ganfield

发明人： Leland Leslie Day ,  Steven Michael Douskey ,  Paul Allen Ganfield

IPC分类号： G01R31/3185 ,  H04B17/00

CPC分类号： G01R31/318541

摘要： A system and method for reducing simultaneous switching during scan-based testing of a system logic design. System logic is divided into clusters of system logic, and one or more scan chains are associated with each logic cluster. Each of the logic clusters are concurrently scan tested, yet circuitry in the scan chains associated with a cluster are triggered at different times than the circuitry in the scan chains of other clusters. Offset scan control signals provide the triggering for the scan chains of different clusters. Release and capture functions are also controlled to reduce simultaneous release and capture switching in different clusters.

摘要翻译： 一种在系统逻辑设计的基于扫描的测试期间减少同时切换的系统和方法。 系统逻辑被分为系统逻辑的集群，并且一个或多个扫描链与每个逻辑集群相关联。 每个逻辑集群被同时扫描测试，但与集群相关联的扫描链中的电路在与其他集群的扫描链中的电路不同的时间被触发。 偏移扫描控制信号为不同簇的扫描链提供触发。 释放和捕获功能也受到控制，以减少不同群集中同时的释放和捕获切换。

公开(公告)号：US6158032A

公开(公告)日：2000-12-05

申请号：US49170

申请日：1998-03-27

申请人： Guy Richard Currier ,  Leland Leslie Day ,  Steven Michael Douskey ,  Paul Allen Ganfield ,  James Maurice Wallin

发明人： Guy Richard Currier ,  Leland Leslie Day ,  Steven Michael Douskey ,  Paul Allen Ganfield ,  James Maurice Wallin

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536

摘要： A data processing system, circuit arrangement, program product, and method thereof utilize a multi-path scan interface that is capable of providing multiple scan paths into a plurality of scan ring segments in an integrated circuit device. The multi-path scan interface utilizes one or more multiplexers coupled between scan in and scan out ports and at least one scan ring segment to provide alternate scan paths depending upon select signals supplied to each multiplexer. With such a configuration, a standardized scan interface may developed for interfacing with a wide variety of scan ring segments, and optionally, for multiple purposes. As a result, the amount of custom circuitry necessary to provide access to scan ring segments is significantly reduced.

摘要翻译： 数据处理系统，电路装置，程序产品及其方法利用能够向集成电路装置中的多个扫描环段提供多条扫描路径的多路径扫描接口。 多路径扫描接口利用耦合在扫描入口和扫描端口中的一个或多个多路复用器和至少一个扫描环段，以根据提供给每个多路复用器的选择信号提供交替的扫描路径。 利用这种配置，可以开发用于与各种各样的扫描环段对接的标准化扫描界面，并且可选地，出于多个目的。 因此，提供访问扫描环段所需的定制电路的量显着减少。

公开(公告)号：US06178534B1

公开(公告)日：2001-01-23

申请号：US09076221

申请日：1998-05-11

申请人： Leland Leslie Day ,  Paul Allen Ganfield

发明人： Leland Leslie Day ,  Paul Allen Ganfield

IPC分类号： G01R3128

CPC分类号： G01R31/3016

摘要： A system and method for conducting a repeatable logic test on at least one functional unit of an IC chip includes steps of selecting at least one functional unit of at least several functional units, propagating test data through a part or all functional units of the time domain; and capturing test data of the selected functional unit. The functional units are either selected or held inactive such that only the selected functional unit is allowed to capture the test results for determining a critical timing path within the selected functional unit and only the functional unit. By selecting different combination of the functional unit(s), a number of the critical timing paths are readily determined in the chip.

摘要翻译： 用于对IC芯片的至少一个功能单元进行可重复逻辑测试的系统和方法包括以下步骤：选择至少一个功能单元的至少一个功能单元，通过时域的部分或全部功能单元传播测试数据 ; 并捕获所选功能单元的测试数据。 功能单元被选择或保持不活动，使得仅允许选择的功能单元捕获用于确定所选择的功能单元内的关键定时路径并且仅限于功能单元的测试结果。 通过选择功能单元的不同组合，可以容易地在芯片中确定许多临界定时路径。

公开(公告)号：US07321950B2

公开(公告)日：2008-01-22

申请号：US11050021

申请日：2005-02-03

申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F13/1647

摘要： A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

摘要翻译： 提出了一种用于在写入存储器系统之后的早期读取中管理写入到读取周转的方法和装置。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US07487318B2

公开(公告)日：2009-02-03

申请号：US11851468

申请日：2007-09-07

申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/161 ,  G06F13/1647

摘要： Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

摘要翻译： 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US07467277B2

公开(公告)日：2008-12-16

申请号：US11348879

申请日：2006-02-07

申请人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

发明人： Melissa Ann Barnum ,  Mark David Bellows ,  Paul Allen Ganfield ,  Lonny Lambrecht ,  Tolga Ozguner

IPC分类号： G06F13/14

CPC分类号： G11C8/18 ,  G06F13/1642 ,  G06F13/1689 ,  Y02D10/14

摘要： The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

摘要翻译： 本发明一般涉及在包含可变系统时钟的系统中操作的存储器控​​制器。 存储器控制器可以与以可变处理器时钟频率工作的处理器交换数据。 然而，存储器控制器可以以恒定的存储器时钟频率执行存储器访问。 可以提供异步缓冲器以跨可变和恒定时钟域传输数据。 为了防止在切换到较低处理器时钟频率时读取缓冲区溢出，存储器控制器可以使存储器定序器静止，并以较慢的速率从定序器调速读取数据。 为了防止在运行中写入数据，存储器控制器的数据流逻辑可以执行握手以确保在执行写访问之前在缓冲器中完全接收到写数据。

公开(公告)号：US20080168206A1

公开(公告)日：2008-07-10

申请号：US11620110

申请日：2007-01-05

申请人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

发明人： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

IPC分类号： G06F13/14

CPC分类号： G06F13/4059

摘要： In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a first memory; (b) a processor adapted to issue a functional command to the first memory; (c) a translation chip; (d) a cache memory coupled to the translation chip; (e) a first link adapted to couple the processor to the translation chip; and (f) a second link adapted to couple the translation chip to the first memory; and (2) calibrating the first link to transmit data between the processor and cache memory. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）第一存储器的计算机系统; （b）适于向第一存储器发出功能命令的处理器; （c）翻译芯片; （d）耦合到所述平移芯片的高速缓冲存储器; （e）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（f）适于将所述翻译芯片耦合到所述第一存储器的第二链路; 和（2）校准第一链路以在处理器和高速缓冲存储器之间传送数据。 提供了许多其他方面。

公开(公告)号：US07617332B2

公开(公告)日：2009-11-10

申请号：US10427865

申请日：2003-05-01

申请人： Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Kerry Christopher Imming ,  John David Irish

发明人： Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Kerry Christopher Imming ,  John David Irish

IPC分类号： G06F3/00 ,  G06F15/16

CPC分类号： H04L29/06 ,  H04L69/12

摘要： A method, apparatus and computer program product are provided for implementing packet command instructions for network processing. A set of packet commands is provided. Each packet command defines a corresponding packet operation. A command from the set of packet commands is issued to perform the defined corresponding packet operation. A packet buffer structure hardware is provided for performing one or more predefined packet manipulation functions responsive to the issued command.

摘要翻译： 提供了一种用于实现用于网络处理的分组命令指令的方法，装置和计算机程序产品。 提供一组分组命令。 每个分组命令定义相应的分组操作。 发出来自该组命令的命令以执行定义的对应的分组操作。 提供了分组缓冲器结构硬件，用于响应于发出的命令执行一个或多个预定义的分组操纵功能。