Vapor transport process for growing selected compound semiconductors of
high purity
    1.
    发明授权
    Vapor transport process for growing selected compound semiconductors of high purity 失效
    用于生长高纯度的选定化合物半导体的蒸气运输过程

    公开(公告)号:US4439266A

    公开(公告)日:1984-03-27

    申请号:US259384

    申请日:1981-05-01

    IPC分类号: C30B23/02 C30B23/06

    摘要: Disclosed herein is a process for growing II-IV semiconductor crystals which includes providing both a II-IV semiconductor source material and a crystal growth support member in a predetermined dynamic vacuum. This vacuum is sufficient to create a predetermined overpressure at the source material and simultaneously remove impurities therefrom. The temperature of the support member is initally raised to a predetermined level above the temperature of the source material to thereby prevent vapor transport between the two. Then, the temperature of the support member is lowered to a predetermined value below that of the source material to produce a disassociation of elemental gases from the source material and initiate controlled vapor transport of the elemental gases from the source material to the support member. In this manner, compound semiconductor crystals of high purity and stoichiometry are formed on the surface of the support member.

    摘要翻译: 本文公开了一种用于生长II-IV半导体晶体的方法,其包括在预定的动态真空中提供II-IV半导体源材料和晶体生长支撑构件。 该真空足以在源材料上产生预定的超压并同时从其中除去杂质。 支撑构件的温度初始升高到高于源材料的温度的预定水平,从而防止两者之间的蒸汽输送。 然后,将支撑构件的温度降低到低于源材料的预定值,以产生元素气体与源材料的分离,并引发元素气体从源材料到支撑构件的受控蒸气输送。 以这种方式,在支撑构件的表面上形成高纯度和化学计量的化合物半导体晶体。

    Vapor transport process for growing selected compound semiconductors of
high purity
    2.
    发明授权
    Vapor transport process for growing selected compound semiconductors of high purity 失效
    用于生长高纯度的选定化合物半导体的蒸气运输过程

    公开(公告)号:US4299649A

    公开(公告)日:1981-11-10

    申请号:US92607

    申请日:1979-11-08

    IPC分类号: C30B23/02 C30B25/02

    摘要: The specification describes a process for growing selected compound semiconductors of high stoichiometry and purity and includes the steps of providing both a dynamic vacuum and a predetermined temperature profile in a container or tube containing a chosen semiconductor source material. The dynamic vacuum is used to create a predetermined minimum overpressure. P.sub.min, in this container with respect to the vapor pressure of the source material, while simultaneously removing impurities through in opening in the container during the crystal growth process. This process involves the vapor transport of elements of the selected compound semiconductor from the source material to a suitable support member, such as a graphite crucible which is maintained at a predetermined uniform controlled temperature. Alternatively, the crystal growth process can be in the form of a vapor phase epitaxial process wherein the selected compound semiconductor is epitaxially deposited on a chosen semiconductor substrate whose temperature is also closely controlled.

    摘要翻译: 本说明书描述了用于生长具有高化学计量和纯度的所选化合物半导体的方法,并且包括在容纳选定的半导体源材料的容器或管中提供动态真空和预定温度分布的步骤。 动态真空用于产生预定的最小超压。 Pmin,相对于源材料的蒸气压在该容器中,同时在晶体生长过程中同时去除容器中的杂质。 该方法涉及将所选择的化合物半导体的元件从源材料蒸汽输送到合适的支撑构件,例如保持在预定的均匀控制温度的石墨坩埚。 或者,晶体生长过程可以是气相外延工艺的形式,其中所选择的化合物半导体外延沉积在温度也受到严格控制的所选择的半导体衬底上。

    Synthesization method of ternary chalcogenides
    3.
    发明授权
    Synthesization method of ternary chalcogenides 失效
    三元硫属化合物的合成方法

    公开(公告)号:US3933990A

    公开(公告)日:1976-01-20

    申请号:US849001

    申请日:1969-08-11

    摘要: Large, strain free, single crystals of high optical quality selected from the IB-VB-VIB and IIIB-VB-VIB ternary chalcogenide groups, having a single stable solid phase from room temperature to the melting point of the crystal and vice-versa, are synthesized by (1) placing stoichiometric quantities of the compound constituents with 3% excess VIB constituent in a two part, sublimation-reaction fused silica tube, the VB constituents being placed in sublimation part, and the remaining constituents being placed in the reaction part, and evacuating and sealing the tube, (2) subliming and purifying the VB constituent and condensing it in the reaction part, which is then cooled and sealed from the sublimation part, (3) reacting, uniting and slowly cooling the reaction part constituents, (4) placing the reacted constituents in fused silica growth tube, which is evacuated, backfilled with helium, and sealed, (5) forming a melt in the upper part of a two part furnace and lowering at about 1.8 mm/hr. through a greater than 100.degree.C temperature gradient, (6) annealing the single crystal in the lower furnace part about one-half the melting point temperature and cooling it to room temperature at about 5.degree.C/hr., and (7) removing the crystal by dissolving the tube in hydrofluoric acid.

    摘要翻译: 选自IB-VB-VIB和IIIB-VB-VIB三元硫属化物基团的大的无应变单晶,具有从室温至晶体熔点的单一稳定固相,反之亦然, 通过(1)将化学计量量的具有3%过量VIB组分的化合物组分放置在两部分升华反应熔融石英管中,将VB组分置于升华部分中,并将剩余组分置于反应部分 (2)升华和净化VB组分并将其冷凝在反应部分中,然后将其从升华部分冷却和密封,(3)使反应部件成分反应,并联并缓慢冷却, (4)将反应的成分置于熔融二氧化硅生长管中,其被抽真空,用氦回填并密封,(5)在两部分炉的上部形成熔体并以约1.8mm / 小时 通过大于100℃的温度梯度,(6)将下炉部分中的单晶退火约为熔点温度的一半,并以约5℃/小时将其冷却至室温,(7)除去 通过将管溶解在氢氟酸中的晶体。

    Wafer base for silicon carbide semiconductor device
    4.
    发明授权
    Wafer base for silicon carbide semiconductor device 失效
    碳化硅半导体器件用晶圆基座

    公开(公告)号:US5010035A

    公开(公告)日:1991-04-23

    申请号:US197582

    申请日:1988-05-13

    IPC分类号: H01L29/24

    摘要: A semiconductor device wafer base wherein devices may be fabricated in silicon carbide, the base having a compatible substrate and a beta silicon carbide overlay layer epitaxially related to the substrate, the beta silicon carbide layer being unpolytyped, single crystal, uncracked, without twins, and having integrated circuit quality surface morphology. Preferably, the substrate is a single crystal of titanium carbide, which is the same cubic lattice-type as beta silicon carbide with a lattice parameter different from that of beta silicon carbide by less than about 1%. Additionally, the thermal expansion coefficients of beta silicon carbide and titanium carbide are nearly the same, minimizing the creation of thermal stresses during cooling and heating. The beta silicon carbide is useful in fabricating semi-conductor devices for use at much higher temperatures than is silicon, and for use at high power levels, at high frequencies, and in radiation hardened applications. The device base may be fabricated by any suitable technique, including reactive deposition and chemical vapor deposition.

    摘要翻译: 一种半导体器件晶片基底,其中器件可以制造在碳化硅中,所述基底具有兼容的衬底和与衬底外延相关的β碳化硅覆层,所述β碳化硅层未折射,单晶,未裂纹,无双胞胎,以及 具有集成电路质量的表面形态。 优选地,基体是碳化钛的单晶,其是与β碳化硅相同的立方晶格型,具有与β碳化硅的晶格参数不同于小于约1%的晶格参数。 此外,β碳化硅和碳化钛的热膨胀系数几乎相同,在冷却和加热期间最小化热应力的产生。 β碳化硅可用于制造比硅高得多的温度使用的半导体器件,并且用于高功率级,高频率和辐射硬化应用。 器件基底可以通过任何合适的技术制造,包括反应沉积和化学气相沉积。

    Wafer base for silicon carbide semiconductor device
    5.
    发明授权
    Wafer base for silicon carbide semiconductor device 失效
    碳化硅半导体器件用晶圆基座

    公开(公告)号:US4767666A

    公开(公告)日:1988-08-30

    申请号:US737367

    申请日:1985-05-23

    CPC分类号: H01L29/1608 Y10T428/263

    摘要: A semiconductor device wafer base wherein devices may be fabricated in silicon carbide, the base having a compatible substrate and a beta silicon carbide overlay layer epitaxially related to the substrate, the beta silicon carbide layer being unpolytyped, single crystal, uncracked, without twins, and having integrated circuit quality surface morphology. Preferably, the substrate is a single crystal of titanium carbide, which is the same cubic lattice-type as beta silicon carbide with a lattice parameter different from that of beta silicon carbide by less than about 1%. Additionally, the thermal expansion coefficients of beta silicon carbide and titanium carbide are nearly the same, minimizing the creation of thermal stresses during cooling and heating. The beta silicon carbide is useful in fabricating semiconductor devices for use at much higher temperatures than is silicon, and for use at high power levels, at high frequencies, and in radiation hardened applications. The device base may be fabricated by any suitable technique, including reactive deposition and chemical vapor deposition.

    摘要翻译: 一种半导体器件晶片基底,其中器件可以制造在碳化硅中,所述基底具有兼容的衬底和与衬底外延相关的β碳化硅覆盖层,β碳化硅层未折射,单晶,未裂纹,无双胞胎,以及 具有集成电路质量的表面形态。 优选地,基体是碳化钛的单晶,其是与β碳化硅相同的立方晶格型,具有与β碳化硅的晶格参数不同于小于约1%的晶格参数。 此外,β碳化硅和碳化钛的热膨胀系数几乎相同,在冷却和加热期间最小化热应力的产生。 β碳化硅可用于制造在比硅高得多的温度下使用的半导体器件,并且用于高功率电平,高频率和辐射硬化应用中。 器件基底可以通过任何合适的技术制造,包括反应沉积和化学气相沉积。

    CMOS integrated microsensor with a precision measurement circuit
    6.
    发明授权
    CMOS integrated microsensor with a precision measurement circuit 失效
    具有精密测量电路的CMOS集成微型传感器

    公开(公告)号:US5659195A

    公开(公告)日:1997-08-19

    申请号:US489023

    申请日:1995-06-08

    摘要: Improved microsensors are provided by combining surface micromachined substrates, including integrated CMOS circuitry, together with bulk micromachined wafer bonded substrates which include at least part of a microelectromechanical sensing element. In the case of an accelerometer, the proof mass is included within the wafer bonded bulk machined substrate, which is bonded to the CMOS surface machine substrate, which has corresponding etch pits defined therein over which the wafer bonded substrate is disposed, and in the case of accelerometer, the proof mass or thin film membranes in the case of other types of detectors such as acoustical detectors or infrared detectors. A differential sensor electrode is suspended over the etch pits so that the parasitic capacitance of the substrate is removed from the capacitance sensor, or in the case of a infrared sensor, to provide a low thermal conductance cavity under the pyroelectric refractory thin film. Where a membrane suspended electrode is utilized over an etch pit, one or more apertures are defined therethrough to avoid squeeze film damping. Accelerometers built according to the methodology are provided with a nulling feedback voltage to maintain the switch DC voltage across sensing capacitors in a null condition and to maintain high sensitivity without requiring either a precision transformer or regulated power sources in the capacitance bridge of the accelerometer.

    摘要翻译: 通过将表面微机械加工的衬底(包括集成的CMOS电路)与包括微机电感测元件的至少一部分的体微米加工的晶片结合的衬底组合来提供改进的微传感器。 在加速度计的情况下,证明质量包括在晶片接合的主体加工衬底内,该衬底被粘合到CMOS表面机器衬底,其具有限定在其中的对应的蚀刻凹坑,晶片接合衬底在其上设置, 在其他类型的检测器(例如声学检测器或红外检测器)的情况下,加速度计,检测质量膜或薄膜膜。 差分传感器电极悬挂在蚀刻凹坑上,使得从电容传感器或者在红外传感器的情况下去除衬底的寄生电容,以在热电耐火薄膜下方提供低导热空腔。 当膜悬浮电极在蚀刻坑上使用时,一个或多个孔被限定在其中以避免挤压膜阻尼。 根据方法构建的加速度计具有归零反馈电压,以将感测电容器两端的开关直流电压保持在零值状态,并且保持高灵敏度,而不需要加速度计的电容桥中的精密变压器或稳压电源。

    Electromagnetic scattering in active guides
    7.
    发明授权
    Electromagnetic scattering in active guides 失效
    主动导轨中的电磁散射

    公开(公告)号:US5090017A

    公开(公告)日:1992-02-18

    申请号:US359770

    申请日:1989-05-31

    IPC分类号: G02F1/377 H01S3/30

    CPC分类号: H01S3/30 G02F1/377

    摘要: Non-normal plane wave electromagnetic scattering from active guiding structures, such as dielectric films, generates large resonances at discrete plane-wave angles of incidance relative to an interface with the active film. These resonances are generated from a "leaky" wave phase matching condition. Enhancement in the scattered field intensities on the order of 100 is achieved using finite diameter pump and probe laser beams and active films as thin as 6 microns. Solid state and dye lasers with unique characteristics are obtained. Oscillators, amplifiers, cyroscopic and nonlinear laser applications employing the active guiding structure or film provide enhanced performance.

    摘要翻译: 来自主动导向结构(例如电介质膜)的非正常平面波电磁散射相对于与活性膜的界面在离散的平面波角发生大的谐振。 这些谐振是从“泄漏”波相位匹配条件产生的。 使用有限直径的泵浦和探针激光束以及6微米的有源膜可实现100级的散射场强度的增强。 获得具有独特特性的固态和染料激光器。 使用主动导向结构或薄膜的振荡器,放大器,光学和非线性激光应用提供了更好的性能。

    Hybrid Brewster's angle wire grid infrared polarizer
    8.
    发明授权
    Hybrid Brewster's angle wire grid infrared polarizer 失效
    混合布鲁斯特角线网红外线偏振器

    公开(公告)号:US4221464A

    公开(公告)日:1980-09-09

    申请号:US952170

    申请日:1978-10-17

    IPC分类号: G02B5/30

    CPC分类号: G02B5/3066 G02B5/3058

    摘要: There is disclosed a polarizer particularly suited for use in the infrared wavelengths which comprises a wire grid polarizer in optically cascaded relationship with a Brewster's Angle Polarizer. Not only do the extinction ratios of the optically cascaded polarizers multiply to provide higher extinction ratios at these wavelengths, but also the reflective mirror properties of the wire grid polarizers can be used in combination with the known optical properties of Brewster Polarizers to provide a combined device which optimizes both the extinction ratios achieved and the balance between the reflection and recombination problem of the system on the one hand and the offset or beam walking problem on the other hand in a manner to provide optical characteristics which are not achievable from any simple combinations of either type of polarizer alone.

    摘要翻译: 公开了一种特别适用于红外波长的偏振器,其包括与布鲁斯特角度偏振器在光学级联关系中的线栅偏振器。 光学级联偏振器的消光比不仅在这些波长处倍增以提供较高的消光比,而且还可以将布线极化器的反射镜特性与布鲁斯特偏振器的已知光学特性结合使用以提供组合装置 其优化了所获得的消光比和系统的反射和复合问题之间的平衡以及偏移或光束行走问题,另一方面提供了通过任何简单组合不能实现的光学特性的方式 任何一种类型的偏振器单独。

    Solar cells arrangement
    9.
    发明授权
    Solar cells arrangement 失效
    太阳能电池的安排

    公开(公告)号:US08354583B2

    公开(公告)日:2013-01-15

    申请号:US12301399

    申请日:2007-05-30

    IPC分类号: H02N6/00 H01L31/042 G02B6/00

    摘要: A solar energy conversion system is presented. The system comprises at least one waveguide arrangement having at least one light input respectively. The waveguide arrangement comprises a core unit for passing input solar radiation therethrough and a cladding material arrangement interfacing with the core therealong. The cladding material arrangement is configured as an array of spaced-apart solar cells arranged along the core unit and having different optical absorption ranges, such that an interface between the waveguide core and the cladding arrangement spectrally splits the photons of the input solar radiation by causing the photons of different wavelengths, while passing through the core unit, to be successively absorbed and thereby converted into electricity by the successive solar cells of said array.

    摘要翻译: 提出了太阳能转换系统。 该系统包括分别具有至少一个光输入的至少一个波导装置。 波导装置包括用于使输入的太阳辐射通过的芯单元和与其相连接的包层材料布置。 包层材料布置被配置为沿着芯单元布置并具有不同光吸收范围的间隔开的太阳能电池阵列,使得波导芯和包层布置之间的界面通过引起输入的太阳辐射光谱分裂光子 不同波长的光子在通过核心单元时被连续吸收,从而由所述阵列的连续太阳能电池转换成电。

    Method and apparatus for intelligent ranging via image subtraction
    10.
    发明授权
    Method and apparatus for intelligent ranging via image subtraction 失效
    通过图像减法进行智能测距的方法和装置

    公开(公告)号:US06711280B2

    公开(公告)日:2004-03-23

    申请号:US09866072

    申请日:2001-05-25

    IPC分类号: G06R900

    摘要: A method and system for ranging an object are disclosed. The method includes illuminating a field of view potentially including the object, synchronously receiving reflected signals from the field of view with and without illumination, capturing first and second images within an array, and generating a subtraction image using the images. One image is captured in the array while the other image is in the array. The first and second images include reflected signals from the field of view with and without illumination, respectively. The array includes first and second groups of lines that are unmasked and masked, respectively. In one exposure, the first group of lines is loaded with the first or second image. The image in the first group of lines is shifted into the second group. In another exposure, the first group of lines is loaded with the other image, which is shifted into the second group.

    摘要翻译: 公开了一种测距对象的方法和系统。 该方法包括照亮潜在地包括对象的视场,在有和没有照明的情况下同步地接收来自视场的反射信号,捕获阵列内的第一和第二图像,以及使用该图像生成减影图像。 一个图像被捕获在阵列中,而另一个图像在数组中。 第一和第二图像分别包括来自具有和不具有照明的视场的反射信号。 该阵列分别包括未屏蔽和屏蔽的第一组和第二组线。 在一次曝光中,第一组线条被装入第一或第二图像。 第一组线中的图像被移入第二组。 在另一曝光中,第一组线被加载另一个图像,该图像被移入第二组。