公开(公告)号：US20070247919A1

公开(公告)日：2007-10-25

申请号：US11701165

申请日：2007-01-31

申请人： Antonino Conte ,  Roberto Annunziata ,  Paola Zuliani

发明人： Antonino Conte ,  Roberto Annunziata ,  Paola Zuliani

IPC分类号： G11C16/06

CPC分类号： G11C16/0433

摘要： A memory architecture includes at least one matrix of memory cells of the EEPROM type organized in rows or word lines and columns or bit lines. Each memory cell includes a floating gate cell transistor and a selection transistor and is connected to a source line shared by the matrix. The memory cells are organized in words, all the memory cells belonging to a same word being driven by a byte switch, which is, in turn, connected to at least one control gate line. The memory cells further have accessible substrate terminals connected to a first additional line.

摘要翻译： 存储器架构包括以行或字线和列或位线组织的EEPROM类型的至少一个存储器单元矩阵。 每个存储单元包括浮栅单元晶体管和选择晶体管，并连接到由矩阵共享的源极线。 存储器单元以字为单位，属于相同字的所有存储单元由字节开关驱动，该字节开关依次连接至至少一个控制栅极线。 存储单元还具有连接到第一附加线路的可访问基板端子。

公开(公告)号：US07649786B2

公开(公告)日：2010-01-19

申请号：US11701165

申请日：2007-01-31

申请人： Antonino Conte ,  Roerto Annunziata ,  Paola Zuliani

发明人： Antonino Conte ,  Roerto Annunziata ,  Paola Zuliani

IPC分类号： G11C16/04

CPC分类号： G11C16/0433

摘要： A memory architecture includes at least one matrix of memory cells of the EEPROM type organized in rows or word lines and columns or bit lines. Each memory cell includes a floating gate cell transistor and a selection transistor and is connected to a source line shared by the matrix. The memory cells are organized in words, all the memory cells belonging to a same word being driven by a byte switch, which is, in turn, connected to at least one control gate line. The memory cells further have accessible substrate terminals connected to a first additional line.

摘要翻译： 存储器架构包括以行或字线和列或位线组织的EEPROM类型的至少一个存储器单元矩阵。 每个存储单元包括浮栅单元晶体管和选择晶体管，并连接到由矩阵共享的源极线。 存储器单元以字为单位，属于相同字的所有存储单元由字节开关驱动，该字节开关依次连接至至少一个控制栅极线。 存储单元还具有连接到第一附加线路的可访问基板端子。

公开(公告)号：US07663927B2

公开(公告)日：2010-02-16

申请号：US11941650

申请日：2007-11-16

申请人： Elisabetta Palumbo ,  Paola Zuliani ,  Roberto Annunziata ,  Daniele Zompi

发明人： Elisabetta Palumbo ,  Paola Zuliani ,  Roberto Annunziata ,  Daniele Zompi

IPC分类号： G11C16/06

CPC分类号： G11C16/28 ,  G11C7/14 ,  H01L27/11519 ,  H01L27/11524

摘要： A reference voltage generator for a matrix of non-volatile memory cells of the EEPROM type, comprises at least one array enabled by an access transistor. The array comprises at least one reference cell associated with a relative select transistor, the transistors and the cell being realized on a semiconductor substrate and having active regions delimited by suitable field oxide regions and covered by a tunnel oxide layer and comprising at least one floating gate realized by a first polysilicon layer and covered by a dielectric layer and by a second polysilicon layer. Advantageously, the floating gate of the reference cells is contacted by a first contact terminal connected to a discharge transistor for the periodical discharge of possibly present charges. A process manufactures such a voltage generator.

摘要翻译： 用于EEPROM类型的非易失性存储器单元的矩阵的参考电压发生器包括由存取晶体管使能的至少一个阵列。 该阵列包括与相对选择晶体管相关联的至少一个参考单元，晶体管和单元被实现在半导体衬底上，并且具有由合适的场氧化物区域限定并被隧道氧化物层覆盖并且包括至少一个浮置栅极 由第一多晶硅层实现并被介电层和第二多晶硅层覆盖。 有利地，参考单元的浮置栅极与连接到放电晶体管的第一接触端子接触，用于可能存在的电荷的周期性放电。 一个工艺制造这样的电压发生器。

公开(公告)号：US20060043461A1

公开(公告)日：2006-03-02

申请号：US11258675

申请日：2005-10-25

申请人： Paola Zuliani ,  Elisabetta Palumbo ,  Marina Scaravaggi ,  Roberto Annunziata

发明人： Paola Zuliani ,  Elisabetta Palumbo ,  Marina Scaravaggi ,  Roberto Annunziata

IPC分类号： H01L29/788 ,  H01L29/76

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps: defining on a same semiconductor substrate respective active areas for the byte selection transistor, for the floating gate transistor and for the selection transistor split by portions of insulating layer; depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer on the whole substrate and a second polysilicon layer, characterised in that it comprises the following steps: removing through a traditional photolithographic technique the multilayer structure to form at least a couple of two bands developing substantially in a parallel way to the columns of the matrix of memory cells, the first band being effective to define the gate regions of the byte selection transistor and of the selection transistor, the second band being effective to define the gate region of the floating gate transistor, a portion of the first band further extending on the portion of insulating layer which is adjacent to the byte selection transistor, forming an opening in the portion up to expose the first polysilicon layer, forming a conductive layer in the opening to put said first polysilicon layer in electric contact with said second polysilicon layer.

摘要翻译： 一种用于制造用于集成在半导体衬底上的行和列组织的非易失性存储器单元的矩阵的字节选择晶体管的处理，每个存储单元包括浮置栅晶体管和选择晶体管，该过程提供以下步骤： 相同的半导体衬底用于字节选择晶体管的相应有效区域，用于浮置栅极晶体管和用于分离绝缘层的选择晶体管; 沉积包括至少栅极氧化物层，第一多晶硅层，整个衬底上的电介质层和第二多晶硅层的多层结构，其特征在于其包括以下步骤：通过传统的光刻技术去除形成的多层结构 至少两个条带基本上以并行方式发展到存储器单元矩阵的列，第一条带有效地限定字节选择晶体管和选择晶体管的栅极区域，第二条带有效地 限定浮栅晶体管的栅极区，第一带的一部分在绝缘层的与字节选择晶体管相邻的部分上进一步延伸，在该部分中形成开口以暴露第一多晶硅层，形成导电 以使所述第一多晶硅层与所述第二多晶硅层电接触。

公开(公告)号：US20080123404A1

公开(公告)日：2008-05-29

申请号：US11941650

申请日：2007-11-16

申请人： Elisabetta Palumbo ,  Paola Zuliani ,  Roberto Annunziata ,  Daniele Zompi

发明人： Elisabetta Palumbo ,  Paola Zuliani ,  Roberto Annunziata ,  Daniele Zompi

IPC分类号： G11C16/28 ,  H01L21/8247

CPC分类号： G11C16/28 ,  G11C7/14 ,  H01L27/11519 ,  H01L27/11524

摘要： A reference voltage generator for a matrix of non-volatile memory cells of the EEPROM type, comprises at least one array enabled by an access transistor. The array comprises at least one reference cell associated with a relative select transistor, the transistors and the cell being realized on a semiconductor substrate and having active regions delimited by suitable field oxide regions and covered by a tunnel oxide layer and comprising at least one floating gate realized by a first polysilicon layer and covered by a dielectric layer and by a second polysilicon layer. Advantageously, the floating gate of the reference cells is contacted by a first contact terminal connected to a discharge transistor for the periodical discharge of possibly present charges. A process manufactures such a voltage generator.

摘要翻译： 用于EEPROM类型的非易失性存储器单元的矩阵的参考电压发生器包括由存取晶体管使能的至少一个阵列。 该阵列包括与相对选择晶体管相关联的至少一个参考单元，晶体管和单元被实现在半导体衬底上，并且具有由合适的场氧化物区域限定并被隧道氧化物层覆盖并且包括至少一个浮置栅极 由第一多晶硅层实现并被介电层和第二多晶硅层覆盖。 有利地，参考单元的浮置栅极与连接到放电晶体管的第一接触端子接触，用于可能存在的电荷的周期性放电。 一个工艺制造这样的电压发生器。

公开(公告)号：US06972454B2

公开(公告)日：2005-12-06

申请号：US10715887

申请日：2003-11-18

申请人： Paola Zuliani ,  Elisabetta Palumbo ,  Marina Scaravaggi ,  Roberto Annunziata

发明人： Paola Zuliani ,  Elisabetta Palumbo ,  Marina Scaravaggi ,  Roberto Annunziata

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： In a matrix of non volatile memory cells integrated on a semiconductor substrate, each memory cell includes a floating gate transistor and a selection transistor formed in a first active area, while each byte includes a byte selection transistor formed in a second active area separated from the first by portions of insulating layer. A portion of a multilayer structure including a gate oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer extends over the byte selection and selection transistors, forming the gate regions thereof, and further extending on a portion of insulating layer. A conductive layer is formed in an opening in the second polysilicon and dielectric layers, over the portion of insulating layer, putting the first polysilicon layer in electric contact with the second polysilicon layer. Another portion of the multiplayer structure comprises the gate region of the floating gate transistor.

摘要翻译： 在集成在半导体衬底上的非易失性存储单元的矩阵中，每个存储单元包括浮置晶体管和形成在第一有源区中的选择晶体管，而每个字节包括形成在与第一有源区分离的第二有源区中的字节选择晶体管 首先是绝缘层的一部分。 包括栅极氧化物层，第一多晶硅层，电介质层和第二多晶硅层的多层结构的一部分在字节选择和选择晶体管上延伸，形成其栅极区域，并且还在绝缘层的一部分上延伸 。 在第二多晶硅和电介质层的开口中，在绝缘层的部分上形成导电层，使第一多晶硅层与第二多晶硅层电接触。 多人结构的另一部分包括浮置栅极晶体管的栅极区域。

公开(公告)号：US07456467B2

公开(公告)日：2008-11-25

申请号：US11258675

申请日：2005-10-25

申请人： Paola Zuliani ,  Elisabetta Palumbo ,  Marina Scaravaggi ,  Roberto Annunziata

发明人： Paola Zuliani ,  Elisabetta Palumbo ,  Marina Scaravaggi ,  Roberto Annunziata

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11524

摘要： A process for manufacturing a matrix of non volatile memory cells includes forming a floating gate transistor and a cell selection transistor in a first active area, and a byte selection transistor in a second active area. A multilayer structure is deposited, comprising a gate oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer. The multilayer structure is defined to form two bands, the first band defining gate regions of the byte selection transistor and the cell selection transistor, and the second band defining the gate region of the floating gate transistor. A portion of the first band extends over a portion of insulating layer adjacent to the byte selection transistor. An opening is formed in the portion of the first band, exposing the first polysilicon layer, and a conductive layer is formed in the opening, electrically coupling the first polysilicon layer with the second polysilicon layer.

摘要翻译： 一种用于制造非易失性存储单元的矩阵的工艺包括在第一有源区中形成浮栅晶体管和单元选择晶体管，以及在第二有源区中形成字节选择晶体管。 沉积多层结构，包括栅极氧化物层，第一多晶硅层，电介质层和第二多晶硅层。 多层结构被定义为形成两个带，第一带限定了字节选择晶体管和单元选择晶体管的栅极区，而第二条限定了浮栅晶体管的栅极区。 第一带的一部分在与字节选择晶体管相邻的绝缘层的一部分上延伸。 在第一带的部分形成开口，露出第一多晶硅层，并且在开口中形成导电层，将第一多晶硅层与第二多晶硅层电耦合。

公开(公告)号：US06949803B2

公开(公告)日：2005-09-27

申请号：US10675245

申请日：2003-09-29

申请人： Paola Zuliani ,  Katia Giarda ,  Roberto Annunziata

发明人： Paola Zuliani ,  Katia Giarda ,  Roberto Annunziata

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/78

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/66575

摘要： A process for fabricating high-voltage drain-extension transistors, whereby the transistors are integrated in a semiconductor substrate along with non-volatile memory cells that include floating gate transistors. The process includes: defining respective active areas for HV transistors and floating gate transistors in a semiconductor substrate, with the active areas separated from each other by insulating regions; forming insulated gate regions of the HV transistors; performing a first dopant implantation to form first portions of the HV transistor junctions; conformably depositing a dielectric layer onto the whole substrate to provide an interpoly layer of the floating gate transistor; making openings at the first portions of the HV transistor junctions; performing, through the openings, a second dopant implantation to form second portions of the high-voltage transistor junctions, with perimeter areas of the gate regions and the active area of the floating gate transistor being screened off by the dielectric layer.

摘要翻译： 一种用于制造高压漏极延伸晶体管的工艺，其中晶体管与包括浮动栅极晶体管的非易失性存储器单元一体地集成在半导体衬底中。 该方法包括：为半导体衬底中的HV晶体管和浮置栅极晶体管定义相应的有源区，其中有源区通过绝缘区彼此分离; 形成HV晶体管的绝缘栅极区域; 执行第一掺杂剂注入以形成HV晶体管结的第一部分; 在整个衬底上顺应地沉积介电层，以提供浮置晶体管的互补层; 在HV晶体管接头的第一部分处形成开口; 通过开口执行第二掺杂剂注入以形成高压晶体管结的第二部分，栅极区域的周边区域和浮置栅极晶体管的有源区域被电介质层屏蔽。

公开(公告)号：US07483296B2

公开(公告)日：2009-01-27

申请号：US11233464

申请日：2005-09-22

申请人： Ferdinando Bedeschi ,  Fabio Pellizzer ,  Augusto Benvenuti ,  Loris Vendrame ,  Paola Zuliani

发明人： Ferdinando Bedeschi ,  Fabio Pellizzer ,  Augusto Benvenuti ,  Loris Vendrame ,  Paola Zuliani

IPC分类号： G11C11/36

CPC分类号： G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  G11C2213/79

摘要： A memory device is proposed. The memory device includes a plurality of memory cells, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element and a bipolar element. The memory device further includes control means for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.

摘要翻译： 提出了一种存储器件。 存储器件包括多个存储器单元，其中每个存储器单元包括存储元件和用于在读取操作或编程操作期间选择相应的存储元件的选择器。 选择器包括单极元件和双极元件。 存储器件还包括控制装置，用于在编程操作期间在读取操作或双极元件期间普遍使能单极元件。

公开(公告)号：US20060202245A1

公开(公告)日：2006-09-14

申请号：US11337787

申请日：2006-01-23

申请人： Paola Zuliani ,  Fabio Pellizzer ,  Roberto Bez

发明人： Paola Zuliani ,  Fabio Pellizzer ,  Roberto Bez

IPC分类号： H01L29/94

CPC分类号： H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： A phase-change memory device, wherein memory cells form a memory array arranged in rows and columns. The memory cells are formed by a MOS selection device and a phase-change region connected to the selection device. The selection device is formed by first and second conductive regions which extend in a semiconductor substrate and are spaced from one another via a channel region, and by an isolated control region connected to a respective row and overlying the channel region. The first conductive region is connected to a connection line extending parallel to the rows, the second conductive region is connected to the phase-change region, and the phase-change region is connected to a respective column. The first connection line is a metal interconnection line and is connected to the first conductive region via a source-contact region made as point contact and distinct from the first connection line.

摘要翻译： 一种相变存储器件，其中存储器单元形成以行和列布置的存储器阵列。 存储单元由连接到选择装置的MOS选择装置和相变区域形成。 选择装置由在半导体衬底中延伸并且经由沟道区彼此间隔开的第一和第二导电区域以及连接到相应行并且覆盖沟道区域的隔离控制区域形成。 第一导电区域连接到与行平行延伸的连接线，第二导电区域连接到相变区域，并且相变区域连接到相应的列。 第一连接线是金属互连线，并且通过作为点接触而不同于第一连接线的源极接触区域连接到第一导电区域。