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1.发明申请Non-volatile memory architecture and method, in particular of the EEPROM type 有权非易失性存储器架构和方法，特别是EEPROM类型公开(公告)号：US20070247919A1
公开(公告)日：2007-10-25
申请号：US11701165
申请日：2007-01-31
IPC分类号： G11C16/06
CPC分类号： G11C16/0433
摘要： A memory architecture includes at least one matrix of memory cells of the EEPROM type organized in rows or word lines and columns or bit lines. Each memory cell includes a floating gate cell transistor and a selection transistor and is connected to a source line shared by the matrix. The memory cells are organized in words, all the memory cells belonging to a same word being driven by a byte switch, which is, in turn, connected to at least one control gate line. The memory cells further have accessible substrate terminals connected to a first additional line.
摘要翻译： 存储器架构包括以行或字线和列或位线组织的EEPROM类型的至少一个存储器单元矩阵。 每个存储单元包括浮栅单元晶体管和选择晶体管，并连接到由矩阵共享的源极线。 存储器单元以字为单位，属于相同字的所有存储单元由字节开关驱动，该字节开关依次连接至至少一个控制栅极线。 存储单元还具有连接到第一附加线路的可访问基板端子。
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2.发明授权Non-volatile memory architecture and method, in particular of the EEPROM type 有权非易失性存储器架构和方法，特别是EEPROM类型公开(公告)号：US07649786B2
公开(公告)日：2010-01-19
申请号：US11701165
申请日：2007-01-31
申请人： Antonino Conte , Roerto Annunziata , Paola Zuliani
发明人： Antonino Conte , Roerto Annunziata , Paola Zuliani
IPC分类号： G11C16/04
CPC分类号： G11C16/0433
摘要： A memory architecture includes at least one matrix of memory cells of the EEPROM type organized in rows or word lines and columns or bit lines. Each memory cell includes a floating gate cell transistor and a selection transistor and is connected to a source line shared by the matrix. The memory cells are organized in words, all the memory cells belonging to a same word being driven by a byte switch, which is, in turn, connected to at least one control gate line. The memory cells further have accessible substrate terminals connected to a first additional line.
摘要翻译： 存储器架构包括以行或字线和列或位线组织的EEPROM类型的至少一个存储器单元矩阵。 每个存储单元包括浮栅单元晶体管和选择晶体管，并连接到由矩阵共享的源极线。 存储器单元以字为单位，属于相同字的所有存储单元由字节开关驱动，该字节开关依次连接至至少一个控制栅极线。 存储单元还具有连接到第一附加线路的可访问基板端子。
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公开(公告)号：US20120250421A1
公开(公告)日：2012-10-04
申请号：US13421322
申请日：2012-03-15
CPC分类号： H02M3/073 , H02M2003/076 , Y10T29/49117
摘要： The charge pump circuit has a plurality of cascaded charge pump stages, each provided with a first pump capacitor connected to a first internal node and receiving a first high voltage phase signal, and a second pump capacitor connected to a second internal node and receiving a second high voltage phase signal, complementary with respect to the first. A first transfer transistor is coupled between the first internal node and an intermediate node, and a second transfer transistor is coupled between the second internal node and the intermediate node. The first and second high voltage phase signals have a voltage dynamics higher than a maximum voltage sustainable by the first and second transfer transistors. A protection stage is set between the first internal node and second internal node and respectively, the first transfer transistor and second transfer transistor, for protecting the same transfer transistors from overvoltages.
摘要翻译： 电荷泵电路具有多个级联的电荷泵级，每个级联电荷泵级设置有连接到第一内部节点并接收第一高电压相位信号的第一泵电容器和连接到第二内部节点并接收第二内部节点的第二泵电容器 高电压相位信号，相对于第一相互补充。 第一传输晶体管耦合在第一内部节点和中间节点之间，并且第二传输晶体管耦合在第二内部节点和中间节点之间。 第一和第二高电压相位信号具有比由第一和第二传输晶体管可持续的最大电压高的电压动态特性。 在第一内部节点和第二内部节点之间设置保护级，分别设置第一传输晶体管和第二传输晶体管，用于保护相同的传输晶体管免受过电压。
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4.发明授权Circuit for generating a temperature-compensated voltage reference, in particular for applications with supply voltages lower than 1V 有权用于产生温度补偿电压基准的电路，特别是用于电源电压低于1V的应用公开(公告)号：US08120415B2
公开(公告)日：2012-02-21
申请号：US12464481
申请日：2009-05-12
CPC分类号： G05F3/30
摘要： An embodiment of a circuit is described for the generation of a temperature-compensated voltage reference of the type comprising at least one generator circuit of a band-gap voltage, inserted between a first and a second voltage reference and including an operational amplifier, having in turn a first and a second input terminal connected to an input stage connected to these first and second input terminal and comprising at least one pair of a first and a second bipolar transistor for the generation of a first voltage component proportional to the temperature. The circuit also comprises the control block connected to the generator circuit of a band-gap voltage in correspondence with at least one first control node which is supplied with a biasing voltage value comprising at least one voltage component which increases with the temperature for compensating the variations of the base-emitter voltage of the first and second bipolar transistors and ensure the turn-on of a pair of input transistors of the operational amplifier. The circuit has an output terminal suitable for supplying a temperature-compensated voltage value obtained by the sum of the first voltage component proportional to the temperature and of a second component inversely proportional to the temperature.
摘要翻译： 描述了电路的实施例，用于生成包括插入在第一和第二参考电压之间并包括运算放大器的带隙电压的至少一个发生器电路的类型的温度补偿电压基准，其具有 转动连接到与这些第一和第二输入端连接的输入级的第一和第二输入端，并且包括至少一对第一和第二双极晶体管，用于产生与温度成比例的第一电压分量。 该电路还包括与至少一个第一控制节点相对应的带隙电压连接到发生器电路的控制块，该至少一个第一控制节点被提供有包括至少一个电压分量的偏置电压值，所述至少一个电压分量随着用于补偿变化的温度而增加 的第一和第二双极晶体管的基极 - 发射极电压，并确保运算放大器的一对输入晶体管的导通。 电路具有适于提供通过与温度成比例的第一电压分量和与温度成反比的第二分量的和获得的温度补偿电压值的输出端子。
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5.发明授权公开(公告)号：US08050106B2
公开(公告)日：2011-11-01
申请号：US12113709
申请日：2008-05-01
申请人： Francesco La Rosa , Antonino Conte
发明人： Francesco La Rosa , Antonino Conte
IPC分类号： G11C16/04
CPC分类号： G11C16/225 , G11C16/102
摘要： A method writes data in a non-volatile memory comprising memory cells that are erased before being written. The method comprises the steps of providing a main non-volatile memory area comprising target pages, providing an auxiliary non-volatile memory area comprising auxiliary pages, providing a look-up table to associate to an address of invalid target page an address of valid auxiliary page, and, in response to a command for writing a piece of data in a target page writing the piece of data as well as the address of the target page in a first erased auxiliary page, invalidating the target page, and updating the look-up table.
摘要翻译： 一种方法是将数据写入非易失性存储器，其中包括在写入之前被擦除的存储器单元。 该方法包括以下步骤：提供包括目标页面的主非易失性存储器区域，提供包括辅助页面的辅助非易失性存储器区域，提供查找表以与无效目标页面的地址相关联的有效辅助地址 页面，并且响应于在目标页面中写入一条数据的命令以及在第一擦除的辅助页面中的目标页面的地址，使目标页面无效，并且更新查找页面， 桌子。
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6.发明授权公开(公告)号：US07576591B2
公开(公告)日：2009-08-18
申请号：US11780206
申请日：2007-07-19
申请人： Antonino Conte , Carmelo Ucciardello , Carmine D'Alessandro , Mario Micciche , Giovanni Matranga , Diego De Costantini
发明人： Antonino Conte , Carmelo Ucciardello , Carmine D'Alessandro , Mario Micciche , Giovanni Matranga , Diego De Costantini
IPC分类号： G05F1/10
摘要： A charge pump system is provided that includes at least one first pump for generating a first working voltage, a second pump for generating a second working voltage, and a third pump for generating a third working voltage. The first pump is connected to an internal supply voltage reference that can having a limited value, and has an output terminal connected to the second and third pumps so as to supplying them with the first working voltage as their supply voltage. A method is also provided for managing the generation of voltages to be used with such a charge pump system.
摘要翻译： 提供一种电荷泵系统，其包括用于产生第一工作电压的至少一个第一泵，用于产生第二工作电压的第二泵和用于产生第三工作电压的第三泵。 第一泵连接到可以具有有限值的内部电源参考电压，并且具有连接到第二和第三泵的输出端，以便向它们提供第一工作电压作为它们的电源电压。 还提供了一种用于管理与这种电荷泵系统一起使用的电压的产生的方法。
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7.发明授权Low-consumption regulator for a charge pump voltage generator and related system and method 有权低功耗稳压器用于电荷泵电压发生器及相关系统及方法公开(公告)号：US07403405B2
公开(公告)日：2008-07-22
申请号：US10877063
申请日：2004-06-24
申请人： Antonino Conte , Enrico Castaldo
发明人： Antonino Conte , Enrico Castaldo
IPC分类号： H02M3/18
CPC分类号： H02M3/073
摘要： A regulator circuit for a charge pump voltage generator includes a voltage comparator circuit that performs a voltage comparison between a charge pump output voltage and a reference voltage. A circuit responsive to the voltage comparator circuit conditions a charge pump clocking to the result of the voltage comparison. The voltage comparator circuit includes a sampling circuit for sampling the charge pump output voltage at a sampling rate. A sampling rate control circuit is responsive to the voltage comparisons for controlling the sampling rate according to the result of the voltage comparison.
摘要翻译： 用于电荷泵电压发生器的调节器电路包括执行电荷泵输出电压和参考电压之间的电压比较的电压比较器电路。 响应于电压比较器电路的电路将电荷泵时钟调节到电压比较的结果。 电压比较器电路包括用于以采样率对电荷泵输出电压进行采样的采样电路。 采样率控制电路响应于电压比较，以根据电压比较的结果控制采样率。
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公开(公告)号：US07170790B2
公开(公告)日：2007-01-30
申请号：US11061104
申请日：2005-02-18
IPC分类号： G11C16/06
摘要： A sensing circuit (120) for sensing currents, including: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V−); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and a comparison current generating circuit (N3s, 135; N3s, 135′; N3s, 135″) for generating the comparison current based on a reference current (Ir). The comparison current generating circuit includes at least one voltage generator (135; 135′; 135″). A memory device using the sensing circuit and a method are also provided.
摘要翻译： 一种用于感测电流的感测电路（120），包括：测量电路分支（132i），具有用于接收待感测的输入电流（Ic）的测量节点，用于将输入电流转换成对应的输入电压（V- ）; 至少一个比较电路分支（132o），具有用于接收比较电流（Igs）的比较节点，用于将比较电流转换成对应的比较电压（V +）; 以及用于比较输入和比较电压的至少一个电压比较器（140）和用于产生比较电流的比较电流产生电路（N 3 s，135; N 3 s，135'; N 3 s，135“） 基于参考电流（Ir）。 比较电流产生电路包括至少一个电压发生器（135; 135'; 135“）。 还提供了使用感测电路的存储器件和方法。
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公开(公告)号：US06927441B2
公开(公告)日：2005-08-09
申请号：US10050427
申请日：2002-01-15
申请人： Domenico Pappalardo , Maurizio Gaibotti , Gaetano Palumbo , Antonino Conte , Stefano Lo Giudice
发明人： Domenico Pappalardo , Maurizio Gaibotti , Gaetano Palumbo , Antonino Conte , Stefano Lo Giudice
CPC分类号： H02M3/07 , H02M2003/077
摘要： A variable charge pump contains several individual simple charge pumps, each with a pumping capacitor and a switching mechanism. Additionally, a switching network is coupled to the individual charge pumps so that the different lines in the charge pump can be connected together in a serial mode or parallel mode (or mixed serial and parallel modes) to match the needs of the output load. The switching network is easily changed to provide the necessary driving capability as the needs of the output load changes.
摘要翻译： 可变电荷泵包含几个单独的简单电荷泵，每个具有泵浦电容器和开关机构。 此外，开关网络耦合到各个电荷泵，使得电荷泵中的不同线路可以以串行模式或并行模式（或混合串行和并行模式）连接在一起以匹配输出负载的需要。 随着输出负载的变化需要，开关网络容易改变以提供必要的驱动能力。
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10.发明授权Method for biasing an EEPROM non-volatile memory array and corresponding EEPROM non-volatile memory device 有权用于偏置EEPROM非易失性存储器阵列和相应的EEPROM非易失性存储器件的方法公开(公告)号：US08376237B2
公开(公告)日：2013-02-19
申请号：US12885028
申请日：2010-09-17
IPC分类号： G06K19/06
CPC分类号： G11C16/0433 , G11C16/10 , G11C16/16
摘要： Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation.
摘要翻译： 这里描述了一种用于偏置由排列成行和列的存储器单元形成的EEPROM阵列的方法，每个可操作地耦合到第一开关和第二开关，并且具有通过第一开关选择性地连接到位线的第一导通端子， 选择性地可连接到通过第二开关的栅极控制线的控制终端，其中与每一行相关联的是分别连接到第一开关的控制端的第一字线和第二字线，以及分别操作地耦合到 同一行的存储单元。 该方法设想为给定的存储器操作选择至少一个存储器单元，偏置与其相关联的行的第一字线和第二字线，并且特别是以彼此不同的电压偏置第一和第二字线并且具有更高的值 而不是内部电源电压，并且是给定存储器操作的函数。
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