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公开(公告)号：US08536689B2
公开(公告)日：2013-09-17
申请号：US11163035
申请日：2005-10-03
IPC分类号： H01L23/495 , H01L21/44
CPC分类号： H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/27013 , H01L2224/29007 , H01L2224/32014 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2224/83385 , H01L2924/00014 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system is provided including an integrated circuit package system including an integrated circuit and a lead frame. The lead frame has a multi-surface die attach pad and the integrated circuit is mounted to the multi-surface die attach pad.
摘要翻译： 提供一种集成电路封装系统，其包括集成电路封装系统，其包括集成电路和引线框架。 引线框架具有多表面管芯连接焊盘，并且集成电路安装到多表面管芯附接焊盘。
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2.发明授权公开(公告)号：US07556987B2
公开(公告)日：2009-07-07
申请号：US11428272
申请日：2006-06-30
IPC分类号： H01L21/00 , H01L23/495 , H01R43/00 , H05K5/02
CPC分类号： H01L23/49503 , H01L21/4828 , H01L23/3107 , H01L23/49548 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/29007 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , Y10T29/49124 , Y10T29/49204 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system is provided including forming a D-ring comprising half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring.
摘要翻译： 提供一种集成电路封装系统，包括形成D形环，其包括半蚀刻桨，蚀刻环和蚀刻连接条。 连杆在桨和环之间。 该系统还包括将集成电路管芯安装在D形环的中心部分上，连接集成电路管芯和D形环，并封装集成电路管芯和D环的一部分。
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3.发明申请INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ETCHED RING AND DIE PADDLE AND METHOD OF MANUFACTURE THEREOF 有权具有蚀刻环和DIE平台的集成电路包装系统及其制造方法公开(公告)号：US20090230529A1
公开(公告)日：2009-09-17
申请号：US12473239
申请日：2009-05-27
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/49503 , H01L21/4828 , H01L23/3107 , H01L23/49548 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/29007 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , Y10T29/49124 , Y10T29/49204 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system is provided including: forming a D-ring includes half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring.
摘要翻译： 提供一种制造集成电路封装系统的方法，包括：形成D环包括半蚀刻桨，蚀刻环和蚀刻连接条。 连杆在桨和环之间。 该系统还包括将集成电路管芯安装在D形环的中心部分上，连接集成电路管芯和D形环，并封装集成电路管芯和D环的一部分。
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4.发明授权Integrated circuit packaging system with etched ring and die paddle and method of manufacture thereof 有权具有蚀刻环和芯片的集成电路封装系统及其制造方法公开(公告)号：US07863108B2
公开(公告)日：2011-01-04
申请号：US12473239
申请日：2009-05-27
IPC分类号： H01L21/00 , H01L23/495 , H01R43/16 , H05K5/02
CPC分类号： H01L23/49503 , H01L21/4828 , H01L23/3107 , H01L23/49548 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/29007 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , Y10T29/49124 , Y10T29/49204 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system is provided including: forming a D-ring includes half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring.
摘要翻译： 提供一种制造集成电路封装系统的方法，包括：形成D环包括半蚀刻桨，蚀刻环和蚀刻连接条。 连杆在桨和环之间。 该系统还包括将集成电路管芯安装在D形环的中心部分上，连接集成电路管芯和D形环，并封装集成电路管芯和D环的一部分。
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公开(公告)号：US20080001263A1
公开(公告)日：2008-01-03
申请号：US11428272
申请日：2006-06-30
IPC分类号： H01L23/495
CPC分类号： H01L23/49503 , H01L21/4828 , H01L23/3107 , H01L23/49548 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/29007 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49171 , H01L2224/73265 , H01L2924/00014 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , Y10T29/49124 , Y10T29/49204 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system is provided including forming a D-ring comprising half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring.
摘要翻译： 提供一种集成电路封装系统，包括形成D形环，其包括半蚀刻桨，蚀刻环和蚀刻连接条。 连杆在桨和环之间。 该系统还包括将集成电路管芯安装在D形环的中心部分上，连接集成电路管芯和D形环，并封装集成电路管芯和D环的一部分。
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公开(公告)号：US07352055B2
公开(公告)日：2008-04-01
申请号：US11562957
申请日：2006-11-22
IPC分类号： H01L23/495
CPC分类号： H01L23/3107 , H01L23/4952 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/11 , H01L2224/1132 , H01L2224/1134 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/13 , H01L2224/13012 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/16245 , H01L2224/81011 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2924/00011 , H01L2924/00014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor package includes a substrate having a plurality of lead fingers. A plurality of stud bumps is attached to the plurality of lead fingers. A die having a plurality solder bumps is provided. The plurality of solder bumps is attached to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps. An encapsulant encapsulates the die, the electrical connections, and the plurality of lead fingers to expose a lower surface of the plurality of lead fingers. The plurality of stud bumps may include a plurality of clusters of stud bumps.
摘要翻译： 半导体封装包括具有多个引线指的基板。 多个螺柱凸起附接到多个引线指。 提供具有多个焊料凸块的模具。 多个焊料凸块被附接到多个柱形凸块以形成多个电连接并且提供多个焊料凸块的受控的倒塌。 密封剂封装模具，电连接和多个引线指，以暴露多个引线指的下表面。 多个凸起凸起可以包括多个螺柱凸块。
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7.发明授权Semiconductor package with controlled solder bump wetting and fabrication method therefor 有权具有受控焊料凸块润湿的半导体封装及其制造方法公开(公告)号：US07148086B2
公开(公告)日：2006-12-12
申请号：US10908120
申请日：2005-04-28
IPC分类号： H01L21/44
CPC分类号： H01L23/3107 , H01L23/4952 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/11 , H01L2224/1132 , H01L2224/1134 , H01L2224/114 , H01L2224/1147 , H01L2224/116 , H01L2224/13 , H01L2224/13012 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/16245 , H01L2224/81011 , H01L2224/81193 , H01L2224/8121 , H01L2224/81815 , H01L2924/00011 , H01L2924/00014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor package and a method of manufacturing a semiconductor package include a substrate having a plurality of lead fingers. A plurality of stud bumps is attached to the plurality of lead fingers. A die having a plurality solder bumps is provided. The plurality of solder bumps is attached to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps. An encapsulant encapsulates the die, the electrical connections, and the plurality of lead fingers to expose a lower surface of the plurality of lead fingers. The plurality of stud bumps may include a plurality of clusters of stud bumps.
摘要翻译： 半导体封装和半导体封装的制造方法包括具有多个引线指的基板。 多个螺柱凸起附接到多个引线指。 提供具有多个焊料凸块的模具。 多个焊料凸块被附接到多个柱形凸块以形成多个电连接并且提供多个焊料凸块的受控的倒塌。 密封剂封装模具，电连接和多个引线指，以暴露多个引线指的下表面。 多个凸起凸起可以包括多个螺柱凸块。
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公开(公告)号：US08421197B2
公开(公告)日：2013-04-16
申请号：US13023244
申请日：2011-02-08
IPC分类号： H01L23/48 , H01L23/50 , H01L23/49 , H01L23/495
CPC分类号： H01L23/4951 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/49513 , H01L23/49548 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/27436 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/83856 , H01L2224/85 , H01L2224/92247 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer.
摘要翻译： 集成电路封装系统包括：半导体芯片; 半导体芯片上的应力消除层; 应力消除层上的粘附层; 以及结合到粘合层的电互连。
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公开(公告)号：US07479692B2
公开(公告)日：2009-01-20
申请号：US11558413
申请日：2006-11-09
IPC分类号： H01L23/495
CPC分类号： H01L23/4334 , H01L23/49548 , H01L23/552 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49171 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： An integrated circuit package system is provided including forming a paddle, forming a ring with a recess in the paddle, mounting a device in the recess, forming a slot in the ring, and mounting a heat sink in the slot over the device.
摘要翻译： 提供了一种集成电路封装系统，包括形成桨叶，在桨中形成具有凹槽的环，将器件安装在凹槽中，在环中形成槽，以及将散热器安装在器件上的槽中。
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公开(公告)号：US20110121466A1
公开(公告)日：2011-05-26
申请号：US13023244
申请日：2011-02-08
CPC分类号： H01L23/4951 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/49513 , H01L23/49548 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/27436 , H01L2224/2919 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/83856 , H01L2224/85 , H01L2224/92247 , H01L2924/00014 , H01L2924/01027 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package system includes: a semiconductor chip; a stress-relieving layer on the semiconductor chip; an adhesion layer on the stress relieving layer; and electrical interconnects bonded to the adhesion layer.
摘要翻译： 集成电路封装系统包括：半导体芯片; 半导体芯片上的应力消除层; 应力消除层上的粘附层; 以及结合到粘合层的电互连。
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