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    Memory with segmented error correction codes
    6.
    发明授权
    Memory with segmented error correction codes 有权
    具有分段纠错码的存储器

    公开(公告)号：US08745472B2

    公开(公告)日：2014-06-03

    申请号：US13602116

    申请日：2012-09-01

    申请人： Manish Goel ,  Dongsuk Jeon

    发明人： Manish Goel ,  Dongsuk Jeon

    IPC分类号： H03M13/00

    CPC分类号： H03M13/6356 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1575 ,  H03M13/2942

    摘要： A code word is received that was derived from a plurality of smaller code words that represent a data word of 2m data bits and a plurality of error correction code bits. The code word is converted into the plurality of smaller code words and syndromes are computed by multiplying each of the plurality of smaller code words by a check matrix. The syndrome words are processed to determine a number of errors that exist in each of the plurality of smaller code words. A portion of the syndrome words is processed to determine locations of possible errors within the plurality of smaller code words. Up to two errors may be corrected and up to three errors may be detected in the code word by using the number of errors and the locations of possible errors to determine erroneous bits in the code word.

    摘要翻译： 接收从代表2m数据位的数据字和多个纠错码位的多个较小码字导出的码字。 码字被转换为多个较小的码字，并且通过将多个较小码字中的每一个乘以一个校验矩阵来计算校正子。 对所述校正子字进行处理以确定存在于所述多个较小码字中的每一个中的多个错误。 处理一部分综合词以确定多个较小码字内的可能误差的位置。 可以纠正多达两个错误，并且可以通过使用错误的数量和可能的错误的位置来确定码字中的错误位来在码字中检测到最多三个错误。

    Memory with Segmented Error Correction Codes
    7.
    发明申请
    Memory with Segmented Error Correction Codes 有权
    具有分段纠错码的存储器

    公开(公告)号：US20140068391A1

    公开(公告)日：2014-03-06

    申请号：US13602116

    申请日：2012-09-01

    申请人： Manish Goel ,  Dongsuk Jeon

    发明人： Manish Goel ,  Dongsuk Jeon

    IPC分类号： H03M13/00

    CPC分类号： H03M13/6356 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/1575 ,  H03M13/2942

    摘要： A code word is received that was derived from a plurality of smaller code words that represent a data word of 2m data bits and a plurality of error correction code bits. The code word is converted into the plurality of smaller code words and syndromes are computed by multiplying each of the plurality of smaller code words by a check matrix. The syndrome words are processed to determine a number of errors that exist in each of the plurality of smaller code words. A portion of the syndrome words is processed to determine locations of possible errors within the plurality of smaller code words. Up to two errors may be corrected and up to three errors may be detected in the code word by using the number of errors and the locations of possible errors to determine erroneous bits in the code word.

    摘要翻译： 接收从代表2m数据位的数据字和多个纠错码位的多个较小码字导出的码字。 码字被转换为多个较小的码字，并且通过将多个较小码字中的每一个乘以一个校验矩阵来计算校正子。 对所述校正子字进行处理以确定存在于所述多个较小码字中的每一个中的多个错误。 处理一部分综合词以确定多个较小码字内的可能误差的位置。 可以纠正多达两个错误，并且可以通过使用错误的数量和可能的错误的位置来确定码字中的错误位来在码字中检测到最多三个错误。

    Reduced complexity Viterbi decoder
    8.
    发明授权
    Reduced complexity Viterbi decoder 有权
    降低复杂性维特比解码器

    公开(公告)号：US08099658B2

    公开(公告)日：2012-01-17

    申请号：US11932591

    申请日：2007-10-31

    申请人： Seok-Jun Lee ,  Srinivas Lingam ,  Anuj Batra ,  Manish Goel

    发明人： Seok-Jun Lee ,  Srinivas Lingam ,  Anuj Batra ,  Manish Goel

    IPC分类号： H03M13/03

    CPC分类号： H03M13/4107 ,  H03M13/6502 ,  H03M13/6583

    摘要： A Viterbi decoder includes a branch metric unit, an add-compare select unit coupled to the branch metric unit, and a trace-back unit coupled to the add-compare select unit. The branch metric unit includes a branch metric computation unit coupled to a thresholder unit. The branch metric computation unit is configured to compute a branch metric. The thresholder unit is configured to compare the branch metric with a threshold value. If the branch metric is greater than the threshold value, the thresholder unit is configured to forward the threshold value to the add-compare select and not forward the branch metric to the add-compare select unit. Implementing such a branch metric ceiling allows for a predictable reduction in the significant bits of calculations in the Viterbi decoder, which allows for reduction of complexity via elimination of gates and storage elements.

    摘要翻译： 维特比解码器包括分支度量单元，耦合到分支度量单元的加法比较选择单元和耦合到加法比较选择单元的追溯单元。 分支度量单元包括耦合到阈值单元的分支度量计算单元。 分支度量计算单元被配置为计算分支度量。 阈值单元被配置为将分支度量与阈值进行比较。 如果分支度量大于阈值，则阈值单元被配置为将阈值转发到加法比较选择，而不将分支度量转发到加法比较选择单元。 实现这样的分支度量顶点允许在维特比解码器中的有效计算的可预测的减少，这允许通过消除门和存储元件来降低复杂度。

    Sharing logic circuitry for a maximum likelihood MIMO decoder and a viterbi decoder
    9.
    发明授权
    Sharing logic circuitry for a maximum likelihood MIMO decoder and a viterbi decoder 有权
    共享用于最大似然MIMO解码器和维特比解码器的逻辑电路

    公开(公告)号：US08059745B2

    公开(公告)日：2011-11-15

    申请号：US12187178

    申请日：2008-08-06

    申请人： Seok-Jun Lee ,  Manish Goel

    发明人： Seok-Jun Lee ,  Manish Goel

    IPC分类号： H04B7/02 ,  H04L1/02

    CPC分类号： H04L27/2647 ,  H03M13/41 ,  H03M13/6306 ,  H03M13/6508 ,  H04L25/03178 ,  H04L2025/03426

    摘要： A receiver system for receiving and decoding modulated communications signals in a multiple-input, multiple-output (MIMO) environment, where the signals are modulated according to Orthogonal Frequency Division Modulation (OFDM). The receiver system includes shared decoder logic circuitry that executes a maximum-likelihood (ML) estimation algorithm in deriving the signals transmitted from the multiple transmitting antennae, as those signals were received over all of the receiving antennae. For a control channel portion of the data frame, the shared decoder logic circuitry applies Viterbi decoding to the transmitted datastreams estimated by the ML estimation algorithm. This sharing of decoder logic reduces the integrated circuit chip area, and also power dissipation, otherwise required in performing these complex decoding functions.

    摘要翻译： 一种用于在多输入多输出（MIMO）环境中接收和解码调制通信信号的接收机系统，其中信号根据正交频分调制（OFDM）进行调制。 接收机系统包括共享解码器逻辑电路，该解码器逻辑电路在导出从多个发送天线发送的信号时执行最大似然（ML）估计算法，因为这些信号在所有接收天线上被接收。 对于数据帧的控制信道部分，共享解码器逻辑电路对由ML估计算法估计的所发送的数据流应用维特比解码。 解码器逻辑的这种共享降低了集成电路芯片面积以及功耗，否则在执行这些复杂的解码功能时是必需的。