High voltage field balance metal oxide field effect transistor (FBM)
    1.
    发明授权
    High voltage field balance metal oxide field effect transistor (FBM) 有权
    高电压场平衡金属氧化物场效应晶体管(FBM)

    公开(公告)号:US08785279B2

    公开(公告)日:2014-07-22

    申请号:US13561523

    申请日:2012-07-30

    IPC分类号: H01L21/336

    摘要: A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    摘要翻译: 一种形成在半导体衬底中的半导体功率器件,包括在由重掺杂区域支撑的轻掺杂区域的顶部附近的半导体衬底的顶表面附近的高掺杂区域。 所述半导体功率器件还包括向所述高掺杂区域开放的源极沟槽,所述源极沟槽填充有与所述顶部表面附近的所述源极区域电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域相反导电性的掺杂剂的掩埋P区。 要强调的是,该摘要被提供以符合要求抽象的规则,允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是,它不会用于解释或限制权利要求的范围或含义。

    Termination of high voltage (HV) devices with new configurations and methods
    3.
    发明授权
    Termination of high voltage (HV) devices with new configurations and methods 有权
    用新的配置和方法终止高压(HV)设备

    公开(公告)号:US08803251B2

    公开(公告)日:2014-08-12

    申请号:US13135982

    申请日:2011-07-19

    IPC分类号: H01L29/06 H01L21/76

    摘要: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

    摘要翻译: 本发明公开了一种设置在半导体衬底中的半导体功率器件,包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽,其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环,其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

    Termination of high voltage (HV) devices with new configurations and methods
    4.
    发明申请
    Termination of high voltage (HV) devices with new configurations and methods 有权
    用新的配置和方法终止高压(HV)设备

    公开(公告)号:US20130020671A1

    公开(公告)日:2013-01-24

    申请号:US13135982

    申请日:2011-07-19

    IPC分类号: H01L29/06 H01L21/76

    摘要: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

    摘要翻译: 本发明公开了一种设置在半导体衬底中的半导体功率器件,包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽,其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环,其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

    TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS
    6.
    发明申请
    TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS 审中-公开
    具有新配置和方法的高压(HV)器件的终止

    公开(公告)号:US20160013267A1

    公开(公告)日:2016-01-14

    申请号:US14329936

    申请日:2014-07-12

    摘要: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

    摘要翻译: 本发明公开了一种设置在半导体衬底中的半导体功率器件,包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽,其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环,其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

    PROCESS METHOD AND STRUCTURE FOR HIGH VOLTAGE MOSFETS
    10.
    发明申请
    PROCESS METHOD AND STRUCTURE FOR HIGH VOLTAGE MOSFETS 有权
    高压MOSFET的工艺方法和结构

    公开(公告)号:US20150060936A1

    公开(公告)日:2015-03-05

    申请号:US14011078

    申请日:2013-08-27

    摘要: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches formed at a top portion of the semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction each having a nonlinear portion comprising a sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

    摘要翻译: 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括形成在半导体衬底的顶部的多个沟槽,其沿着纵向方向横向跨越半导体衬底延伸,每个具有非线性部分,该非线性部分包括垂直于沟槽的纵向方向的侧壁,并且垂直向下延伸 顶面到沟槽底面。 半导体功率器件还包括设置在沟槽底表面下方的沟槽底部掺杂剂区域和沿着垂直侧壁设置的侧壁掺杂剂区域,其中侧壁掺杂剂区域沿着沟槽的垂直侧壁垂直向下延伸以到达沟槽底部掺杂剂区域, 将沟槽底部掺杂剂区域拾取到半导体衬底的顶表面。