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    METHOD FOR MAKING GATE-OXIDE WITH STEP-GRADED THICKNESS IN TRENCHED DMOS DEVICE FOR REDUCED GATE-TO-DRAIN CAPACITANCE
    3.
    发明申请
    METHOD FOR MAKING GATE-OXIDE WITH STEP-GRADED THICKNESS IN TRENCHED DMOS DEVICE FOR REDUCED GATE-TO-DRAIN CAPACITANCE 审中-公开
    用于制造具有步进厚度的栅极氧化物的方法，用于降低栅极 - 漏电电容的固化DMOS器件

    公开(公告)号：US20130224919A1

    公开(公告)日：2013-08-29

    申请号：US13406814

    申请日：2012-02-28

    Applicant: Yongping Ding ,  Sik Lui ,  Anup Bhalla

    Inventor： Yongping Ding ,  Sik Lui ,  Anup Bhalla

    IPC: H01L21/336

    CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734

    Abstract: A method for making gate-oxide with step-graded thickness (S-G GOX) in a trenched DMOS device is proposed. First, a substrate is provided and a silicon oxide-silicon nitride-silicon oxide (ONO) protective composite layer is formed atop. Second, an upper interim trench (UIT), an upper trench protection wall (UTPW) and a lower interim trench (LIT) are created into the substrate. Third, the substrate material surrounding the LIT is shaped and oxidized into a desired thick-oxide-layer of thickness T1 and depth D1. Fourth, previously formed UTPW is stripped off from the device in progress, then a thin-gate-oxide of thickness T2 where T2

    Abstract translation: 提出了一种在沟槽DMOS器件中制造具有阶梯分级厚度（S-G GOX）的栅极氧化物的方法。 首先，设置基板，在顶部形成氧化硅 - 氮化硅 - 氧化硅（ONO）保护复合层。 第二，在衬底中产生上部中间沟槽（UIT），上沟槽保护壁（UTPW）和下部临时沟槽（LIT）。 第三，围绕LIT的衬底材料成形并氧化成厚度T1和深度D1的所需厚氧化物层。 第四，先前形成的UTPW从正在进行的器件剥离，然后在UIT的垂直表面上形成T2

    Power MOSFET device with self-aligned integrated Schottky and its manufacturing method
    5.
    发明授权
    Power MOSFET device with self-aligned integrated Schottky and its manufacturing method 有权
    功率MOSFET器件具有自对准集成肖特基及其制造方法

    公开(公告)号：US08252648B2

    公开(公告)日：2012-08-28

    申请号：US12826591

    申请日：2010-06-29

    Applicant: Yeeheng Lee ,  Yongping Ding ,  John Chen

    Inventor： Yeeheng Lee ,  Yongping Ding ,  John Chen

    IPC: H01L21/336

    CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782

    Abstract: A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.

    Abstract translation: 功率MOSFET器件及其制造方法包括以下步骤：在接触沟槽的底部的中间区域选择性地沉积第一导电材料，并与光掺杂的N型外延层接触以形成肖特基结，并沉积第二导电材料 导电材料在接触沟槽的侧壁和底角处并与P型重掺杂体区域接触以形成欧姆结。 第一和第二导电材料可以分别优化欧姆接触和肖特基接触的性能而不折不扣。 同时，接触沟槽的角部被P型重掺杂区域围绕，从而有效地减少了在接触沟槽的拐角处积聚的漏电流。

    A PROCESS METHOD AND STRUCTURE FOR HIGH VOLTAGE MOSFETS
    6.
    发明申请
    A PROCESS METHOD AND STRUCTURE FOR HIGH VOLTAGE MOSFETS 有权
    高压MOSFET的工艺方法和结构

    公开(公告)号：US20140332844A1

    公开(公告)日：2014-11-13

    申请号：US13892191

    申请日：2013-05-10

    Applicant: Yongping Ding ,  Lei Zhang ,  Hong Chang ,  Jongoh Kim ,  John Chen

    Inventor： Yongping Ding ,  Lei Zhang ,  Hong Chang ,  Jongoh Kim ,  John Chen

    IPC: H01L21/265 ,  H01L29/78 ,  H01L29/739

    CPC classification number: H01L29/78 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7827

    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

    Abstract translation: 本发明公开了一种设置在半导体衬底中的半导体功率器件。 半导体功率器件包括多个沟槽，每个沟槽具有沟槽端点，端点侧壁垂直于沟槽的纵向方向并且从顶表面垂直向下延伸到沟槽底表面。 半导体功率器件还包括设置在沟槽底表面下方的沟槽底部掺杂剂区域和沿端点侧壁设置的侧壁掺杂剂区域，其中侧壁掺杂剂区域沿着沟槽的端点侧壁垂直向下延伸以到达沟槽底部掺杂剂区域，并且 将沟槽底部掺杂剂区域拾取到半导体衬底的顶表面。

    Power MOSFET Device with Self-Aligned Integrated Schottky Diode
    9.
    发明申请
    Power MOSFET Device with Self-Aligned Integrated Schottky Diode 有权
    具有自对准集成肖特基二极管的功率MOSFET器件

    公开(公告)号：US20120292692A1

    公开(公告)日：2012-11-22

    申请号：US13559502

    申请日：2012-07-26

    Applicant: Yeeheng Lee ,  Yongping Ding ,  John Chen

    Inventor： Yeeheng Lee ,  Yongping Ding ,  John Chen

    IPC: H01L29/786

    CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/782

    Abstract: A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.

    Abstract translation: 功率MOSFET器件及其制造方法包括以下步骤：在接触沟槽的底部的中间区域选择性地沉积第一导电材料，并与光掺杂的N型外延层接触以形成肖特基结，并沉积第二导电材料 导电材料在接触沟槽的侧壁和底角处并与P型重掺杂体区域接触以形成欧姆结。 第一和第二导电材料可以分别优化欧姆接触和肖特基接触的性能而不折不扣。 同时，接触沟槽的角部被P型重掺杂区域围绕，从而有效地减少了在接触沟槽的拐角处积聚的漏电流。

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