公开(公告)号：US20130020671A1

公开(公告)日：2013-01-24

申请号：US13135982

申请日：2011-07-19

申请人： Yeehang Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

发明人： Yeehang Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

公开(公告)号：US08803251B2

公开(公告)日：2014-08-12

申请号：US13135982

申请日：2011-07-19

申请人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

发明人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

公开(公告)号：US08785279B2

公开(公告)日：2014-07-22

申请号：US13561523

申请日：2012-07-30

申请人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

发明人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

IPC分类号： H01L21/336

CPC分类号： H01L29/0634 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 一种形成在半导体衬底中的半导体功率器件，包括在由重掺杂区域支撑的轻掺杂区域的顶部附近的半导体衬底的顶表面附近的高掺杂区域。 所述半导体功率器件还包括向所述高掺杂区域开放的源极沟槽，所述源极沟槽填充有与所述顶部表面附近的所述源极区域电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域相反导电性的掺杂剂的掩埋P区。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20160372542A9

公开(公告)日：2016-12-22

申请号：US14329936

申请日：2014-07-12

申请人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

发明人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/761 ,  H01L29/78

CPC分类号： H01L29/0623 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

公开(公告)号：US20160013267A1

公开(公告)日：2016-01-14

申请号：US14329936

申请日：2014-07-12

申请人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

发明人： Yeeheng Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC分类号： H01L29/06 ,  H01L21/761 ,  H01L29/78

CPC分类号： H01L29/0623 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

公开(公告)号：US20140027841A1

公开(公告)日：2014-01-30

申请号：US13561523

申请日：2012-07-30

申请人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

发明人： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0634 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

公开(公告)号：US09478646B2

公开(公告)日：2016-10-25

申请号：US13192385

申请日：2011-07-27

申请人： Anup Bhalla ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

发明人： Anup Bhalla ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

IPC分类号： H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/7395 ,  H01L21/2636 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/66333

摘要： A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

摘要翻译： 用于制造阳极短路场效应绝缘栅双极晶体管（IGBT）的方法包括选择性地形成具有相反导电类型的第一和第二半导体注入区。 可以将第二导电类型的场阻挡层生长到衬底或植入衬底中。 外延层可以在衬底上或场停止层上生长。 在外延层内形成一个或多个绝缘栅双极晶体管（IGBT）元件单元。

公开(公告)号：US20130200451A1

公开(公告)日：2013-08-08

申请号：US13364948

申请日：2012-02-02

申请人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

发明人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.

摘要翻译： 半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。 在轻掺杂层中形成一个或多个器件。 每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。 每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。 体区与轻掺杂层和重掺杂层具有相反的导电类型。 源区域靠近上表面形成。 在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。 触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

公开(公告)号：US08785278B2

公开(公告)日：2014-07-22

申请号：US13364948

申请日：2012-02-02

申请人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

发明人： Hamza Yilmaz ,  Daniel Ng ,  Daniel Calafut ,  Madhur Bobde ,  Anup Bhalla ,  Ji Pan ,  Yeeheng Lee ,  Jongoh Kim

IPC分类号： H01L21/331

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.

摘要翻译： 半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。 在轻掺杂层中形成一个或多个器件。 每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。 每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。 体区与轻掺杂层和重掺杂层具有相反的导电类型。 源区域靠近上表面形成。 在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。 触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

公开(公告)号：US20160005809A1

公开(公告)日：2016-01-07

申请号：US14298537

申请日：2014-06-06

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L29/06 ,  H01L21/761

CPC分类号： H01L29/0634 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/6609 ,  H01L29/861

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.