公开(公告)号：US08105895B2

公开(公告)日：2012-01-31

申请号：US12932163

申请日：2011-02-17

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L21/8234

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

摘要翻译： 本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。 每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。 分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。 每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。 每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

公开(公告)号：US08471332B2

公开(公告)日：2013-06-25

申请号：US13349288

申请日：2012-01-12

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

公开(公告)号：US20080265312A1

公开(公告)日：2008-10-30

申请号：US12217092

申请日：2008-06-30

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

摘要翻译： 本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。 每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。 分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。 每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。 每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

公开(公告)号：US20140374823A1

公开(公告)日：2014-12-25

申请号：US13925776

申请日：2013-06-24

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L29/78

CPC分类号： H01L29/7803 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

摘要翻译： 本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。 每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。 分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。 每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。 每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

公开(公告)号：US20110140194A1

公开(公告)日：2011-06-16

申请号：US12932163

申请日：2011-02-17

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

摘要翻译： 本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。 每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。 分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。 每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。 每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

公开(公告)号：US07952139B2

公开(公告)日：2011-05-31

申请号：US12217092

申请日：2008-06-30

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

摘要翻译： 本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。 每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。 分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。 每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。 每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

公开(公告)号：US20130009238A1

公开(公告)日：2013-01-10

申请号：US13349288

申请日：2012-01-12

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L27/06 ,  H01L21/329

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

摘要翻译： 本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。 每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。 分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。 每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。 每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

公开(公告)号：US20100163846A1

公开(公告)日：2010-07-01

申请号：US12319164

申请日：2008-12-31

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

公开(公告)号：US07667264B2

公开(公告)日：2010-02-23

申请号：US10952231

申请日：2004-09-27

申请人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

发明人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device comprises a drain, a body in contact with the drain, the body having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a trench extending through the source and the body to the drain, and a gate disposed in the trench, having a gate top surface that extends substantially above the body top surface. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.

摘要翻译： 半导体器件包括漏极，与漏极接触的主体，主体具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中，延伸穿过源和主体的沟槽 并且设置在沟槽中的门具有大致在主体顶表面上方延伸的门顶表面。 一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量 延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

公开(公告)号：US20130221430A1

公开(公告)日：2013-08-29

申请号：US13594837

申请日：2012-08-26

申请人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

发明人： Hamza Yilmaz ,  Daniel Ng ,  Lingpeng Guan ,  Anup Bhalla ,  Wilson Ma ,  Moses Ho ,  John Chen

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7322 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

摘要翻译： 本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。 每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙 每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。 在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。