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    Telemetry Push Aggregation
    1.
    发明公开
    Telemetry Push Aggregation 审中-公开

    公开(公告)号：US20240160267A1

    公开(公告)日：2024-05-16

    申请号：US18510525

    申请日：2023-11-15

    Applicant: Apple Inc.

    Inventor： Doron Rajwan ,  Karl Daniel Wulcan ,  Lital Levy-Rubin ,  Tal Kuzi

    IPC: G06F1/3206 ,  G06F11/30 ,  G06F11/34

    CPC classification number: G06F1/3206 ,  G06F11/3003 ,  G06F11/3062 ,  G06F11/3495

    Abstract: Systems, apparatuses, and methods for implementing telemetry push aggregation techniques are described. A computing system includes one or more input/output (I/O) agents interposed between functional units and a communication fabric. A given I/O agent receives a set of aggregation rules from a power management unit. The I/O agent monitors traffic from the functional units, and the I/O agent generates telemetry data from the traffic data based on the set of aggregation rules. The telemetry data is used by the power management unit to make adjustments to one or more power settings.

    Temperature control loop for integrated circuit
    2.
    发明授权
    Temperature control loop for integrated circuit 有权

    公开(公告)号：US11822399B2

    公开(公告)日：2023-11-21

    申请号：US17387376

    申请日：2021-07-28

    Applicant: Apple Inc.

    Inventor： Doron Rajwan ,  Tal Kuzi ,  Keith Cox ,  Yizhang Yang

    IPC: G06F1/20 ,  G06F11/30 ,  G06F1/08

    CPC classification number: G06F1/206 ,  G06F1/08 ,  G06F11/3058

    Abstract: A temperature control apparatus is disclosed. An integrated circuit (IC) includes a plurality of temperature sensors, a first thermal control loop, and a second thermal control loop. The first thermal control loop is configured to control temperature of the IC by reducing a frequency of a clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a first temperature threshold. The second thermal control loop is configured to control temperature of the IC by dithering the clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a second temperature threshold that is greater than the first temperature threshold.

    Power consumption control based on random bus inversion
    3.
    发明公开
    Power consumption control based on random bus inversion 审中-公开

    公开(公告)号：US20230281154A1

    公开(公告)日：2023-09-07

    申请号：US17683396

    申请日：2022-03-01

    Applicant: Apple Inc.

    Inventor： Doron Rajwan ,  Lior Zimet ,  Sagi Lahav

    IPC: G06F15/78 ,  G06F13/40

    CPC classification number: G06F15/7807 ,  G06F13/4013

    Abstract: An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.

    Data-enable mask compression on a communication bus
    4.
    发明授权
    Data-enable mask compression on a communication bus 有权

    公开(公告)号：US10911267B1

    公开(公告)日：2021-02-02

    申请号：US16845865

    申请日：2020-04-10

    Applicant: Apple Inc.

    Inventor： Luca O. Iuliano ,  Doron Rajwan ,  Ali Rabbani Rankouhi

    IPC: H04L25/02 ,  H04L1/00 ,  H04L25/49

    Abstract: An apparatus includes an encoding circuit, and a communication bus having conductive traces configured to transfer a data payload, including a control signal and up to a maximum number of data words. The encoding circuit is configured to receive an uncompressed data payload and a mask value, and to create, using the mask value, the control signal, the control signal indicative of whether the uncompressed data payload includes one or more non-enabled data words. In response to a determination that the control signal indicates that the uncompressed data payload includes one or more non-enabled data words, the encoding circuit is configured to create a compressed data payload from the uncompressed data payload, and to send, to a decoding circuit, the compressed data payload and the control signal via the plurality of conductive traces of the communication bus. The compressed data payload includes the mask value.

    System-on-chip with DVFM protection circuit
    5.
    发明授权
    System-on-chip with DVFM protection circuit 有权

    公开(公告)号：US12228989B2

    公开(公告)日：2025-02-18

    申请号：US18522324

    申请日：2023-11-29

    Applicant: Apple Inc.

    Inventor： Doron Rajwan ,  Ami Schwartzman ,  Lior Zimet

    IPC: G06F1/28

    Abstract: A system includes multiple hardware circuits and protection circuitry. The multiple hardware circuits are coupled to respective power domains having respective sets of domain-specific power settings. The protection circuitry is configured to monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings, to determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions, and to initiate a responsive action upon detecting that any of the system-level combinations in the subset is specified as invalid.

    Quality-of-Service-Based Fabric Power Management
    6.
    发明申请
    Quality-of-Service-Based Fabric Power Management 有权

    公开(公告)号：US20250044844A1

    公开(公告)日：2025-02-06

    申请号：US18365783

    申请日：2023-08-04

    Applicant: Apple Inc.

    Inventor： Doron Rajwan ,  Alexander Gendler ,  Daniel U. Becker ,  Saher Odeh ,  Ilya Granovsky ,  Lior Zimet

    IPC: G06F1/26

    Abstract: Techniques are disclosed relating to selective rate limiting and reducing clock frequency of fabric circuitry in response to certain power management events. Disclosed techniques may advantageously allow power management circuitry to reduce or avoid negative impacts of power events by reducing the clock frequency of a communication fabric while using rate limiting of relatively lower-priority traffic to reduce impacts of the frequency reduction on high-priority traffic. For example, rate limiting of lower-quality-of-service virtual channels may continue after recovery of the clock frequency until higher-quality-of-service virtual channels have recovered from the frequency reduction.

    System-on-Chip with DVFM Protection Circuit
    8.
    发明公开
    System-on-Chip with DVFM Protection Circuit 审中-公开

    公开(公告)号：US20240201766A1

    公开(公告)日：2024-06-20

    申请号：US18522324

    申请日：2023-11-29

    Applicant: Apple Inc.

    Inventor： Doron Rajwan ,  Ami Schwartzman ,  Lior Zimet

    IPC: G06F1/28

    CPC classification number: G06F1/28

    Abstract: A system includes multiple hardware circuits and protection circuitry. The multiple hardware circuits are coupled to respective power domains having respective sets of domain-specific power settings. The protection circuitry is configured to monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings, to determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions, and to initiate a responsive action upon detecting that any of the system-level combinations in the subset is specified as invalid.

    Multi-die power management in SoCs
    10.
    发明授权
    Multi-die power management in SoCs 有权

    公开(公告)号：US11693472B2

    公开(公告)日：2023-07-04

    申请号：US17676668

    申请日：2022-02-21

    Applicant: Apple Inc.

    Inventor： Ilya Granovsky ,  Doron Rajwan ,  Tal Kuzi ,  Nir Leshem ,  Lior Zimet

    IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3206

    CPC classification number: G06F1/324 ,  G06F1/3206

    Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Certain techniques include the implementation of rate control circuits to control a clock rate for circuits associated with a communication fabric in an integrated circuit. The clock rate may be reduced based trigger signals received from power delivery trigger circuits coupled to the integrated circuit and voltage regulators providing power to the integrated circuit. Additional techniques may include the use of rate limiter circuits in a memory pipeline.

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