公开(公告)号：US20230299001A1

公开(公告)日：2023-09-21

申请号：US17655716

申请日：2022-03-21

Applicant: Apple Inc.

Inventor： Sambasivan Narayan ,  Praveen Raghavan

IPC: H01L23/528 ,  H01L29/417

CPC classification number: H01L23/5286 ,  H01L29/4175

Abstract: A standard cell layout that may be implemented in FinFET devices or nanosheet FET devices is disclosed. The standard cell layout includes power supply connections from both a topside metal layer and a backside metal layer. A device in the standard cell may be connected to both the topside metal layer and the backside metal layer. Source/drain regions of the device may be connected the metal layers using via contacts within the standard cell layout. Connections to power supply rails from the topside metal layer and the backside metal layer may also be included in the standard cell layout. The rails may be connected to a power supply such that the power supply provides power to the device through both the topside and backside metal layers.

公开(公告)号：US20230299068A1

公开(公告)日：2023-09-21

申请号：US17655678

申请日：2022-03-21

Applicant: Apple Inc.

Inventor： Sambasivan Narayan ,  Praveen Raghavan

IPC: H01L27/02 ,  H01L27/11 ,  H01L23/522 ,  G11C5/06

CPC classification number: H01L27/0207 ,  H01L27/1116 ,  H01L27/1104 ,  H01L27/1108 ,  H01L23/5226 ,  G11C5/063

Abstract: A cell layout that may be implemented in FinFET devices or other FET devices is disclosed. The cell layout includes a control signal route that passes from a first device into backside layers and then underneath a second device. The control signal route then routes back to topside metal layers through inactive transistors that are implemented as via structures on the other side of the second device. Connection to the gate of the second device may then be completed through the topside metal layers. The disclosed control signal route provides a low resistance path that reduces RC delay in the devices in the cell layout.

公开(公告)号：US20250113593A1

公开(公告)日：2025-04-03

申请号：US18524529

申请日：2023-11-30

Applicant: Apple Inc.

Inventor： Praveen Raghavan

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Various integrated circuit transistor device structures that implement nanosheet fin transistors are disclosed. Layouts for the transistor device structures include active cells with dummy cells positioned between active cells. The active cells and dummy cells may include nanosheet fin regions that have different widths. In certain instances, the transitions between different nanosheet fin regions widths (e.g., jogs in the widths) are positioned inside the dummy cells rather than at interfaces between the dummy cells and the active cells. Placing the jogs in widths inside the dummy cells reduces mechanical stresses between active cells and dummy cells and allows for design changes in the size of active transistors during a manufacturing process.

公开(公告)号：US20250107177A1

公开(公告)日：2025-03-27

申请号：US18524600

申请日：2023-11-30

Applicant: Apple Inc.

Inventor： Praveen Raghavan

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Various structures that implement nanosheet transistors are disclosed. The various structures include nanosheet transistors with different widths inside a transistor device. Variation of the width of nanosheet transistors within a transistor device allows for different designs of the input stage and the output stage of the transistor device that may improve power utilization and performance of the transistor device. In some instances, the input stage has nanosheet transistors with smaller width nanosheet fins than nanosheet transistors in the output stage. Variations in nanosheet transistor width may also be implemented within the input stage or the output stage by merging of nanosheet fins.

公开(公告)号：US20240105727A1

公开(公告)日：2024-03-28

申请号：US18448746

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Xin Miao ,  Praveen Raghavan ,  Thomas Hoffmann ,  Saurabh P. Sinha

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11851 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include cells that form inverter devices, NAND devices, and MUX (multiplexer) devices. The disclosed cells include two or four vertical transistors with various connections made to the transistors that include either connected gate logic for inverter and NAND devices or disconnected gate logic for MUX devices.

公开(公告)号：US20240105617A1

公开(公告)日：2024-03-28

申请号：US18448715

申请日：2023-08-11

Applicant: Apple Inc.

Inventor： Xin Miao ,  Praveen Raghavan ,  Thomas Hoffmann

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/42376 ,  H01L29/7827

Abstract: Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include a building block cell with a metal contact layer between the backside metal routing and the vertical transistors. Various connections can be made within the building block cell to form more complex structures such as, but not limited to, inverter devices, NAND devices, and MUX (multiplexer) devices.