公开(公告)号：US20210351344A1

公开(公告)日：2021-11-11

申请号：US17379780

申请日：2021-07-19

Applicant: Applied Materials, Inc.

Inventor： Hsin-wei TSENG ,  Chando PARK ,  Jaesoo AHN ,  Lin XUE ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01L27/22

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

公开(公告)号：US20210119119A1

公开(公告)日：2021-04-22

申请号：US17112484

申请日：2020-12-04

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chando PARK ,  Chi Hong CHING ,  Jaesoo AHN ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01F10/32 ,  H01L43/02 ,  G11C11/16 ,  H01L43/10 ,  H01F41/32 ,  C23C14/06 ,  C23C14/54

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a magnetic tunnel junction (MTJ) device structure includes a junction structure disposed on a substrate, the junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a dielectric capping layer disposed on the junction structure, a metal capping layer disposed on the junction structure, and a top buffer layer disposed on the metal capping layer.

公开(公告)号：US20210143323A1

公开(公告)日：2021-05-13

申请号：US16681351

申请日：2019-11-12

Applicant: Applied Materials, Inc.

Inventor： Jong Mun KIM ,  Minrui YU ,  Chando PARK ,  Mang-Mang LING ,  Jaesoo AHN ,  Chentsau Chris YING ,  Srinivas D. NEMANI ,  Mahendra PAKALA ,  Ellie Y. YIEH

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.

公开(公告)号：US20200161541A1

公开(公告)日：2020-05-21

申请号：US16195313

申请日：2018-11-19

Applicant: Applied Materials, Inc.

Inventor： Hsin-wei TSENG ,  Chando PARK ,  Jaesoo AHN ,  Lin XUE ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01L27/22

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

公开(公告)号：US20230389441A1

公开(公告)日：2023-11-30

申请号：US18231414

申请日：2023-08-08

Applicant: Applied Materials, Inc.

Inventor： Minrui YU ,  Wenhui WANG ,  Jaesoo AHN ,  Jong Mun KIM ,  Sahil PATEL ,  Lin XUE ,  Chando PARK ,  Mahendra PAKALA ,  Chentsau Chris YING ,  Huixiong DAI ,  Christopher S. NGAI

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10N50/10 ,  G01R33/098 ,  G11C11/161 ,  G01R33/095 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

公开(公告)号：US20200161542A1

公开(公告)日：2020-05-21

申请号：US16290621

申请日：2019-03-01

Applicant: Applied Materials, Inc.

Inventor： Jaesoo AHN ,  Chando PARK ,  Hsin-wei TSENG ,  Lin XUE ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/02

Abstract: The bottom-pinned spin-orbit torque (SOT) MRAM devices are fabricated to form high quality interfaces between layers including the spin-orbit torque (SOT) layer and the free layer of the magnetic tunnel junction (MTJ) by forming those layers under vacuum, without breaking vacuum in between formation of the layers. An encapsulation layer is used as an etch stop and to protect the free layer. The encapsulation layer is etched back prior to the deposition of a metal layer. The metal layer forms a plurality of metal lines that are electrically connected to two or more sides of the SOT layer and are electrically coupled to the SOT layer to transfer current through the SOT layer. The metal lines are not in contact with a top surface of the SOT layer which has a dielectric layer disposed thereon.

公开(公告)号：US20220115439A1

公开(公告)日：2022-04-14

申请号：US17423435

申请日：2020-01-16

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chando PARK ,  Jaesoo AHN ,  Hsin-wei TSENG ,  Mahendra PAKALA

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Implementations of the present disclosure generally relate to a memory device. More specifically, implementations described herein generally relate to a SOT-MRAM. The SOT-MRAM includes a memory cell having a magnetic storage layer disposed side by side and in contact with a SOT layer. The side by side magnetic storage layer and the SOT layer can achieve the switching of the magnetic storage layer by reversing the direction of the electrical current flowing through the SOT layer without any additional conditions.

公开(公告)号：US20210351342A1

公开(公告)日：2021-11-11

申请号：US16871779

申请日：2020-05-11

Applicant: Applied Materials, Inc.

Inventor： Minrui YUI ,  Wenhui WANG ,  Jaesoo AHN ,  Jong Mun KIM ,  Sahil PATEL ,  Lin XUE ,  Chando PARK ,  Mahendra PAKALA ,  Chentsau Chris YING ,  Huixiong DAI ,  Christopher S. Ngai

IPC: H01L43/08 ,  H01L43/04 ,  H01L43/14 ,  H01L43/10 ,  G11C11/16 ,  H01L27/22 ,  G01R33/09

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.