公开(公告)号：US11380801B2

公开(公告)日：2022-07-05

申请号：US17006261

申请日：2020-08-28

Applicant: Applied Materials, Inc.

Inventor： Jianheng Li ,  Lai Zhao ,  Yujia Zhai ,  Soo Young Choi

IPC: H01L29/786 ,  H01L21/02 ,  H01L51/05 ,  H01L27/12 ,  H01L29/45 ,  H01L27/32 ,  H01L29/66

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm−2 eV−1 to about 5e11 cm−2 eV−1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

公开(公告)号：US10748759B2

公开(公告)日：2020-08-18

申请号：US16248265

申请日：2019-01-15

Applicant: Applied Materials, Inc.

Inventor： Jianheng Li ,  Lai Zhao ,  Soo Young Choi

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66

Abstract: The present disclosure relates to an improved large area substrate semiconductor device having a high density passivation layer, and method of fabrication thereof. More specifically, a high density SiN passivation layer is formed by plasma enhanced chemical vapor deposition of silane and nitrogen gases at low temperatures. Argon is added as a diluent gas in order to increase SiN passivation layer film density and overall film quality.

公开(公告)号：US10804408B2

公开(公告)日：2020-10-13

申请号：US16143786

申请日：2018-09-27

Applicant: Applied Materials, Inc.

Inventor： Jianheng Li ,  Lai Zhao ,  Yujia Zhai ,  Soo Young Choi

IPC: H01L29/786 ,  H01L21/02 ,  H01L51/05 ,  H01L27/12 ,  H01L29/45 ,  H01L27/32 ,  H01L29/66

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm−2eV−1 to about 5e11 cm−2eV−1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

公开(公告)号：US11670722B2

公开(公告)日：2023-06-06

申请号：US17805161

申请日：2022-06-02

Applicant: Applied Materials, Inc.

Inventor： Jianheng Li ,  Lai Zhao ,  Yujia Zhai ,  Soo Young Choi

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/45 ,  H01L27/32 ,  H01L51/05 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L27/1225 ,  H01L27/3244 ,  H01L29/45 ,  H01L51/0512 ,  H01L51/0525 ,  H01L29/66969 ,  H01L2227/323

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm−2eV−1 to about 5e11 cm−2eV−1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

公开(公告)号：US12021152B2

公开(公告)日：2024-06-25

申请号：US18307846

申请日：2023-04-27

Applicant: Applied Materials, Inc.

Inventor： Jianheng Li ,  Lai Zhao ,  Yujia Zhai ,  Soo Young Choi

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/45 ,  H10K10/46 ,  H10K59/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L27/1225 ,  H01L29/45 ,  H10K10/462 ,  H10K10/472 ,  H10K59/12 ,  H01L29/66969 ,  H10K59/1201

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm−2 eV−1 to about 5e11 cm−2 eV−1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

公开(公告)号：US10923327B2

公开(公告)日：2021-02-16

申请号：US16052304

申请日：2018-08-01

Applicant: Applied Materials, Inc.

Inventor： Jianheng Li ,  Lai Zhao ,  Robin L. Tiner ,  Allen K. Lau ,  Gaku Furuta ,  Soo Young Choi

IPC: H01J37/32 ,  C23C16/505

Abstract: Embodiments described herein generally relate to apparatus and methods for processing a substrate utilizing a high radio frequency (RF) power. The high RF power enables deposition of films on the substrate with more desirable properties. A first plurality of insulating members is disposed on a plurality of brackets and extends laterally inward from a chamber body. A second plurality of insulating members is disposed on the chamber body and extends from the first plurality of insulating members to a support surface of the chamber body. The insulating members reduce the occurrence of arcing between the plasma and the chamber body.