公开(公告)号：US12076763B2

公开(公告)日：2024-09-03

申请号：US16007876

申请日：2018-06-13

Applicant: Applied Materials, Inc.

Inventor： Yujia Zhai ,  Lai Zhao ,  Xiangxin Rui ,  Dong-Kil Yim ,  Tae Kyung Won ,  Soo Young Choi

IPC: B08B7/00 ,  B08B9/00 ,  C23C16/44 ,  H01J37/32 ,  H01L21/02 ,  H01L21/687 ,  H01L27/12 ,  H01L29/49 ,  H01L49/02

CPC classification number: B08B7/0035 ,  B08B9/00 ,  C23C16/4405 ,  H01J37/32082 ,  H01L27/1255 ,  H01L29/4908 ,  H01J2237/335 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/68742 ,  H01L28/40

Abstract: In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material. The high-k dielectric material is selected from zirconium dioxide (ZrO2) and hafnium dioxide (HfO2). The coating material includes a compound selected from alumina (Al2O3), yttrium-containing compounds, and combinations thereof.

公开(公告)号：US11894396B2

公开(公告)日：2024-02-06

申请号：US17647404

申请日：2022-01-07

Applicant: Applied Materials, Inc.

Inventor： Xiangxin Rui ,  Lai Zhao ,  Jrjyan Jerry Chen ,  Soo Young Choi ,  Yujia Zhai

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1248 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/247 ,  H01L29/66969 ,  H01L29/78693

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

公开(公告)号：US11670722B2

公开(公告)日：2023-06-06

申请号：US17805161

申请日：2022-06-02

Applicant: Applied Materials, Inc.

Inventor： Jianheng Li ,  Lai Zhao ,  Yujia Zhai ,  Soo Young Choi

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/45 ,  H01L27/32 ,  H01L51/05 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L27/1225 ,  H01L27/3244 ,  H01L29/45 ,  H01L51/0512 ,  H01L51/0525 ,  H01L29/66969 ,  H01L2227/323

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm−2eV−1 to about 5e11 cm−2eV−1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

公开(公告)号：US12080725B2

公开(公告)日：2024-09-03

申请号：US18221285

申请日：2023-07-12

Applicant: Applied Materials, Inc.

Inventor： Xiangxin Rui ,  Lai Zhao ,  Jrjyan Jerry Chen ,  Soo Young Choi ,  Yujia Zhai

IPC: H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L49/02

CPC classification number: H01L27/1255 ,  H01L27/1222 ,  H01L27/1237 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L28/55 ,  H01L29/4908 ,  H01L29/78675

Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

公开(公告)号：US11380801B2

公开(公告)日：2022-07-05

申请号：US17006261

申请日：2020-08-28

Applicant: Applied Materials, Inc.

Inventor： Jianheng Li ,  Lai Zhao ,  Yujia Zhai ,  Soo Young Choi

IPC: H01L29/786 ,  H01L21/02 ,  H01L51/05 ,  H01L27/12 ,  H01L29/45 ,  H01L27/32 ,  H01L29/66

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm−2 eV−1 to about 5e11 cm−2 eV−1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

公开(公告)号：US11239258B2

公开(公告)日：2022-02-01

申请号：US15773640

申请日：2017-07-11

Applicant: Applied Materials, Inc.

Inventor： Xiangxin Rui ,  Lai Zhao ,  Jrjyan Jerry Chen ,  Soo Young Choi ,  Yujia Zhai

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

公开(公告)号：US11145683B2

公开(公告)日：2021-10-12

申请号：US15648167

申请日：2017-07-12

Applicant: Applied Materials, Inc.

Inventor： Xiangxin Rui ,  Lai Zhao ,  Jrjyan Jerry Chen ,  Soo Young Choi ,  Yujia Zhai

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/49 ,  H01L29/786

Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

公开(公告)号：US11049887B2

公开(公告)日：2021-06-29

申请号：US15889047

申请日：2018-02-05

Applicant: Applied Materials, Inc.

Inventor： Xiangxin Rui ,  Soo Young Choi ,  Shinichi Kurita ,  Yujia Zhai ,  Lai Zhao

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/786 ,  H01L29/49 ,  H01L21/02 ,  H01J37/32 ,  C23C16/40 ,  C23C16/50 ,  C23C16/455 ,  C23C16/52 ,  C23C16/56 ,  H01L21/687 ,  H01L21/67 ,  H01L27/32

Abstract: Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile.

公开(公告)号：US10804408B2

公开(公告)日：2020-10-13

申请号：US16143786

申请日：2018-09-27

Applicant: Applied Materials, Inc.

Inventor： Jianheng Li ,  Lai Zhao ,  Yujia Zhai ,  Soo Young Choi

IPC: H01L29/786 ,  H01L21/02 ,  H01L51/05 ,  H01L27/12 ,  H01L29/45 ,  H01L27/32 ,  H01L29/66

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm−2eV−1 to about 5e11 cm−2eV−1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

公开(公告)号：US12148766B2

公开(公告)日：2024-11-19

申请号：US18545810

申请日：2023-12-19

Applicant: Applied Materials, Inc.

Inventor： Xiangxin Rui ,  Lai Zhao ,  Jrjyan Jerry Chen ,  Soo Young Choi ,  Yujia Zhai

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.