公开(公告)号：US20230343643A1

公开(公告)日：2023-10-26

申请号：US17868475

申请日：2022-07-19

申请人： Applied Materials, Inc.

发明人： Chih-Hsun HSU ,  Shiyu YUE ,  Wei LEI ,  Yi XU ,  Jiang LU ,  Yu LEI ,  Ziye XIONG ,  Tsung-Han YANG ,  Zhimin QI ,  Aixi ZHANG ,  Jie ZHANG ,  Liqi WU ,  Rongjun WANG ,  Shihchung CHEN ,  Meng-Shan WU ,  Chun-Chieh WANG ,  Annamalai LAKSHMANAN ,  Yixiong YANG ,  Xianmin TANG

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76877 ,  H01L21/76876 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L21/76826

摘要： A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

公开(公告)号：US20240363407A1

公开(公告)日：2024-10-31

申请号：US18309669

申请日：2023-04-28

申请人： Applied Materials, Inc.

发明人： Jie ZHANG ,  Liqi WU ,  Cory LAFOLLETT ,  Tsung-Han YANG ,  Wei WENG ,  Qihao ZHU ,  Jiang LU ,  Rongjun WANG ,  Xianmin TANG

IPC分类号： H01L21/768 ,  H01L21/02

CPC分类号： H01L21/76877 ,  H01L21/02274 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76883

摘要： Embodiments of the present disclosure generally relate to a method for forming an electrically conductive feature on a substrate. In one embodiment, the method includes forming a first conductive layer via physical vapor deposition (PVD) in an opening of a substrate. The first conductive layer has a thickness of less than 20 angstroms. The method further includes forming a second conductive layer via PVD on the first conductive layer. The first conductive layer and the second conductive layer are formed at a temperature of less than 50° C. The method further includes annealing at least a portion of the first conductive layer and the second conductive layer.