公开(公告)号：US20240420947A1

公开(公告)日：2024-12-19

申请号：US18210651

申请日：2023-06-16

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Jiajie CEN ,  Sahil Jaykumar PATEL ,  Zhimin QI ,  Ju Hyun OH ,  Aixi ZHANG ,  Xingyao GAO ,  Wei LEI ,  Yi XU ,  Yu LEI ,  Tsung-Han YANG ,  Xiaodong WANG ,  Xiangjin XIE ,  Yixiong YANG ,  Kevin KASHEFI ,  Rongjun WANG

IPC: H01L21/02 ,  H01L21/311

Abstract: A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl5, MoCl6) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.

公开(公告)号：US20240088071A1

公开(公告)日：2024-03-14

申请号：US17944596

申请日：2022-09-14

Applicant: Applied Materials, Inc.

Inventor： Yi XU ,  Yu LEI ,  Zhimin QI ,  Aixi ZHANG ,  Xianyuan ZHAO ,  Wei LEI ,  Xingyao GAO ,  Shirish A. PETHE ,  Tao HUANG ,  Xiang CHANG ,  Patrick Po-Chun LI ,  Geraldine VASQUEZ ,  Dien-yeh WU ,  Rongjun WANG

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L2224/03452 ,  H01L2224/03845 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05157 ,  H01L2224/05184 ,  H01L2924/01027 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/0496 ,  H01L2924/059 ,  H01L2924/35121

Abstract: Methods for reducing resistivity of metal gapfill include depositing a conformal layer in an opening of a feature and on a field of a substrate with a first thickness of the conformal layer of approximately 10 microns or less, depositing a non-conformal metal layer directly on the conformal layer at a bottom of the opening and directly on the field using an anisotropic deposition process. A second thickness of the non-conformal metal layer on the field and on the bottom of the feature is approximately 30 microns or greater. And depositing a metal gapfill material in the opening of the feature and on the field where the metal gapfill material completely fills the opening without any voids.

公开(公告)号：US20240014072A1

公开(公告)日：2024-01-11

申请号：US18212352

申请日：2023-06-21

Applicant: Applied Materials, Inc.

Inventor： Tsung-Han YANG ,  Zhimin QI ,  Yongqian GAO ,  Rongjun WANG ,  Yi XU ,  Yu LEI ,  Xingyao GAO ,  Chih-Hsun HSU ,  Xi CEN ,  Wei LEI ,  Shiyu YUE ,  Aixi ZHANG ,  Kai WU ,  Xianmin TANG

IPC: H01L21/768 ,  H01J37/32

CPC classification number: H01L21/76879 ,  H01J37/32449 ,  H01J37/32816 ,  H01J37/32422 ,  H01J2237/2001 ,  H01J37/321 ,  H01J2237/332

Abstract: A method of forming a semiconductor device structure includes forming a nucleation layer within at least one feature. The method includes exposing the nucleation layer to a nitrogen plasma treatment. The nitrogen plasma treatment preferentially treats the top field and sidewalls while leaving the bottom surface substantially untreated to encourage bottom up metal growth.

公开(公告)号：US20230420295A1

公开(公告)日：2023-12-28

申请号：US18133102

申请日：2023-04-11

Applicant: Applied Materials, Inc.

Inventor： Tsung-Han YANG ,  Xingyao GAO ,  Shiyu YUE ,  Chih-Hsun HSU ,  Shirish PETHE ,  Rongjun WANG ,  Yi XU ,  Wei LEI ,  Yu LEI ,  Aixi ZHANG ,  Xianyuan ZHAO ,  Zhimin QI ,  Jiang LU ,  Xianmin TANG

IPC: H01L21/768 ,  H01L21/285 ,  H01J37/32

CPC classification number: H01L21/76877 ,  H01L21/76876 ,  H01L21/76865 ,  H01L21/2855 ,  H01J2237/338 ,  H01L21/76856 ,  H01L21/76861 ,  H01J37/32899 ,  H01L21/76843

Abstract: A method and apparatus for tungsten gap-fill in semiconductor devices are provided. The method includes performing a gradient oxidation process to oxidize exposed portions of a liner layer, wherein the gradient oxidation process preferentially oxidizes an overhang portion of the liner layer, which obstructs or blocks top openings of one or more features formed within a field region of a substrate. The method further includes performing an etchback process to remove or reduce the oxidized overhang portion of the liner layer, exposing the liner layer to a chemical vapor transport (CVT) process to remove metal oxide remaining from the gradient oxidation process and the etchback process, and performing a tungsten gap-fill process to fill or partially fill the one or more features.

公开(公告)号：US20240371771A1

公开(公告)日：2024-11-07

申请号：US18423437

申请日：2024-01-26

Applicant: Applied Materials, Inc.

Inventor： Sahil Jaykumar PATEL ,  Wei LEI ,  Tuerxun AILIHUMAER ,  Joung Joo LEE ,  Rongjun WANG ,  Xianmin TANG

IPC: H01L23/532 ,  H01L21/768

Abstract: Embodiments of the disclosure include an apparatus and method of forming a semiconductor structure that includes metal contacts with a low resistance. In some embodiments, the semiconductor device generally includes an interconnect. The interconnect generally includes a dielectric layer with a tungsten (W) plug formed therein, a feature formed in the dielectric layer and over the W plug, a liner layer formed on an exposed surface of the W plug and on sidewalls of the feature, an interruption layer formed on the liner layer, and a conductive material substantially filling the feature. The liner layer includes molybdenum (Mo) or W, and the interruption layer includes Mo.

公开(公告)号：US20240087955A1

公开(公告)日：2024-03-14

申请号：US18241343

申请日：2023-09-01

Applicant: Applied Materials, Inc.

Inventor： Yi XU ,  Xianyuan ZHAO ,  Zhimin QI ,  Aixi ZHANG ,  Geraldine VASQUEZ ,  Dien-Yeh WU ,  Wei LEI ,  Xingyao GAO ,  Shirish PETHE ,  Wenting HOU ,  Chao DU ,  Tsung-Han YANG ,  Kyoung-Ho BU ,  Chen-Han LIN ,  Jallepally RAVI ,  Yu LEI ,  Rongjun WANG ,  Xianmin TANG

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876

Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.

公开(公告)号：US20250006518A1

公开(公告)日：2025-01-02

申请号：US18753006

申请日：2024-06-25

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Wei LEI ,  Yu LEI ,  Ju Hyun OH ,  Zhimin QI ,  Sahil Jaykumar PATEL ,  Yi XU ,  Aixi ZHANG ,  Bingqian LIU ,  Cong TRINH ,  Xianmin TANG ,  Hayrensa ABLAT

IPC: H01L21/67 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments herein relate to a method, semiconductor device structures, and multi-chamber processing system for exposing a semiconductor device structure to an oxidizing plasma to form an oxide layer on at least one electrical connection formed in at least one feature formed within a dielectric layer of the semiconductor device structure, performing an etch process to remove the oxide layer and form an etch recess between a portion of the electrical connection and the dielectric layer At least a portion of the etch recess extends underneath at least a portion of the dielectric layer, and filling the at least one feature and the etch recess with a metal material.

公开(公告)号：US20240355673A1

公开(公告)日：2024-10-24

申请号：US18136970

申请日：2023-04-20

Applicant: Applied Materials, Inc.

Inventor： Wei LEI ,  Sahil PATEL ,  Yixiong YANG ,  Yu LEI ,  Shiyu YUE ,  Yi XU ,  Tuerxun AILIHUMAER ,  Juhyun OH ,  Xianmin TANG ,  Rongjun WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  C23C14/18 ,  H01L21/02063 ,  H01L21/28568

Abstract: Semiconductor devices and methods for molybdenum fill in semiconductor devices are provided. In one aspect, a method for processing a semiconductor device substrate is provided. The method includes exposing at least one feature formed in a dielectric layer to a grain modification layer deposition process to deposit a grain modification layer over at least a portion of the at least one feature. The at least one feature is defined by sidewall surfaces formed in the dielectric layer and a bottom surface extending between the sidewall surfaces. The method further includes exposing the at least one feature to a molybdenum deposition process to form a molybdenum-fill layer on the grain modification layer, wherein the grain modification layer comprises a metal different from molybdenum.

公开(公告)号：US20240145300A1

公开(公告)日：2024-05-02

申请号：US17977411

申请日：2022-10-31

Applicant: Applied Materials, Inc.

Inventor： Sahil PATEL ,  Wei LEI ,  Xingyao GAO ,  Shirish A. PETHE ,  Yu LEI

IPC: H01L21/768 ,  H01L21/3205 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/76841 ,  H01L21/32051 ,  H01L21/67017 ,  H01L21/67706

Abstract: Methods and apparatus for processing a substrate are provided. In some embodiments, a method includes: depositing a metal buffer layer on a substrate and within a feature disposed in a dielectric layer of the substrate. The buffer layer is deposited using a first physical vapor deposition (PVD) process at a chamber pressure of less than 500 mTorr while applying less than or equal to 0.08 watts/cm2 of RF bias power to the substrate if the chamber pressure is less than or equal to 3 mTorr and applying less than or equal to 0.8 watts/cm2 of RF bias power to the substrate if the chamber pressure is greater than 3 mTorr. A metal liner layer is deposited atop the buffer layer using a second PVD process at a chamber pressure of less than or equal to 3 mTorr while applying greater than 0.08 watts/cm2 of RF bias power to the substrate.

公开(公告)号：US20230023235A1

公开(公告)日：2023-01-26

申请号：US17477413

申请日：2021-09-16

Applicant: Applied Materials, Inc.

Inventor： Xi CEN ,  Yun TAEWOONG ,  Shirish A. PETHE ,  Kai WU ,  Nobuyuki SASAKI ,  Wei LEI

IPC: H01L21/768

Abstract: Embodiments of methods and associated apparatus for filling a feature in a substrate are provided herein. In some embodiments, a method of filling a feature in a substrate includes: depositing a seed layer of tungsten nitride in the feature via a physical vapor deposition (PVD) process; depositing a liner layer of tungsten on the seed layer of tungsten nitride in the feature via a PVD process; and subsequently filling the feature with a tungsten bulk fill via a chemical vapor deposition (CVD) process.