ASPECT RATIO DEPENDENT ETCH (ARDE) LAG REDUCTION PROCESS BY SELECTIVE OXIDATION WITH INERT GAS SPUTTERING
    1.
    发明申请
    ASPECT RATIO DEPENDENT ETCH (ARDE) LAG REDUCTION PROCESS BY SELECTIVE OXIDATION WITH INERT GAS SPUTTERING 有权
    通过选择性氧化与惰性气体喷射的比例依赖性蚀刻(ARDE)LAG减少过程

    公开(公告)号:US20150064919A1

    公开(公告)日:2015-03-05

    申请号:US14072430

    申请日:2013-11-05

    Abstract: Embodiments of methods for etching a substrate include exposing the substrate to a first plasma formed from an inert gas; exposing the substrate to a second plasma formed from an oxygen-containing gas to form an oxide layer on a bottom and sides of a low aspect ratio feature and a high aspect ratio feature, wherein the oxide layer on the bottom of the low aspect ratio feature is thicker than on the bottom of the high aspect ratio feature; etching the oxide layer from the bottom of the low and high aspect ratio features with a third plasma to expose the bottom of the high aspect ratio feature while the bottom of the low aspect ratio feature remains covered; and exposing the substrate to a fourth plasma formed from a halogen-containing gas to etch the bottom of the low aspect ratio feature and the high aspect ratio feature.

    Abstract translation: 用于蚀刻衬底的方法的实施例包括将衬底暴露于由惰性气体形成的第一等离子体; 将衬底暴露于由含氧气体形成的第二等离子体以在低纵横比特征和高纵横比特征的底部和侧面上形成氧化物层,其中低纵横比特征的底部上的氧化物层 比高宽比特征的底部厚; 使用第三等离子体从低和高纵横比特征的底部蚀刻氧化物层,以暴露高纵横比特征的底部,而低纵横比特征的底部保持覆盖; 并将衬底暴露于由含卤素气体形成的第四等离子体,以蚀刻低纵横比特征和高纵横比特征的底部。

    COMPONENT FOR SEMICONDUCTOR PROCESS CHAMBER HAVING SURFACE TREATMENT TO REDUCE PARTICLE EMISSION
    3.
    发明申请
    COMPONENT FOR SEMICONDUCTOR PROCESS CHAMBER HAVING SURFACE TREATMENT TO REDUCE PARTICLE EMISSION 审中-公开
    用于具有表面处理以减少颗粒排放的半导体工艺室的组件

    公开(公告)号:US20160056059A1

    公开(公告)日:2016-02-25

    申请号:US14832671

    申请日:2015-08-21

    Abstract: Examples of the disclosure generally relate to a component for use in a semiconductor process chamber includes a body having machined surfaces including a first surface and a second surface. The first surface is configured to interface with a support member of the semiconductor process chamber. The second surface is configured to face a processing region of the semiconductor process chamber. A treated area of the second surface includes relatively flatter peaks than an untreated area of the machined surfaces and exhibits an average roughness between 1 and 30 micro-inches.

    Abstract translation: 本公开的实例一般涉及用于半导体处理室的部件,其包括具有包括第一表面和第二表面的加工表面的主体。 第一表面被配置为与半导体处理室的支撑构件相接合。 第二表面被配置为面对半导体处理室的处理区域。 第二表面的处理区域包括比加工表面的未处理区域相对平坦的峰值,并且表现出1至30微英寸之间的平均粗糙度。

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