公开(公告)号：US20180330943A1

公开(公告)日：2018-11-15

申请号：US15976519

申请日：2018-05-10

Applicant: Applied Materials, Inc.

Inventor： Rohit MISHRA ,  Yongjia LI ,  Mir Abdulla AL GALIB ,  Minoru TAKAHASHI ,  Masato ITO ,  Jinhan CHOI

IPC: H01L21/02 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: H01L21/02063 ,  H01L21/02057 ,  H01L21/02661 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: In an embodiment, a method of processing a substrate includes introducing a first process gas or a mixture of the first process gas and a second process gas into an etch chamber; exposing the substrate to the first process gas or to the mixture of the first and second process gases, the substrate having halogen residue formed on an exposed surface, the substrate having high aspect ratio features; forming and maintaining a plasma of the first process gas or a plasma of the mixture of the first and second process gases in the etch chamber to remove the residue from the surface by applying a first source power; exposing the substrate to the second process gas; and forming and maintaining a plasma of the second process gas in the etch chamber to remove the residue from the surface by applying a second source power and a bias power

公开(公告)号：US20160307742A1

公开(公告)日：2016-10-20

申请号：US14690121

申请日：2015-04-17

Applicant: Applied Materials, Inc.

Inventor： Rohit MISHRA ,  Graeme Jamieson SCOTT ,  Khalid Mohiuddin SIRAJUDDIN ,  Sheshraj L. TULSHIBAGWALE ,  Sriskantharajah THIRUNAVUKARASU

IPC: H01J37/32

CPC classification number: H01J37/32642 ,  H01J37/32009 ,  H01J37/321 ,  H01J37/32477 ,  H01J37/32715

Abstract: Embodiments of the present disclosure include methods and apparatuses utilized to reduce residual film layers from a substrate periphery region, such as an edge or bevel of the substrate. Contamination of the substrate bevel, backside and substrate periphery region may be reduced after a plasma process. In one embodiment, an edge ring includes a base circular ring having an inner surface defining a center opening formed thereon and an outer surface defining a perimeter of the base circular ring. The base circular ring includes an upper body and a lower portion connected to the upper body. A step is formed at the inner surface of the base circular ring and above a first upper surface of the upper body. The step defines a pocket above the first upper surface of the upper body. A plurality of raised features formed on the first upper surface of the base circular ring.

Abstract translation: 本公开的实施例包括用于从衬底周边区域（例如衬底的边缘或斜面）减少残余膜层的方法和装置。 在等离子体处理之后，衬底斜面，背面和衬底周边区域的污染可能会降低。 在一个实施例中，边缘环包括基部圆环，其具有限定其上形成的中心开口的内表面和限定基部圆环的周边的外表面。 基座圆环包括上身和连接到上身的下部。 在基部圆环的内表面和上身的第一上表面上方形成台阶。 该步骤限定在上身的第一上表面上方的口袋。 形成在基部圆环的第一上表面上的多个凸起特征。

公开(公告)号：US20140199833A1

公开(公告)日：2014-07-17

申请号：US14148385

申请日：2014-01-06

Applicant: Applied Materials, Inc.

Inventor： Rohit MISHRA ,  Khalid Mohiuddin SIRAJUDDIN ,  Madhava Rao YALAMANCHILI ,  Sonal A. SRIVASTAVA

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/3065

Abstract: The present disclosure provides methods for via reveal etching process to form through-silicon vias (TSVs) in a substrate. In one embodiment, a method for performing a via reveal process to form through-silicon vias in a substrate includes providing a substrate having partial through-silicon vias formed from a first surface of the substrate into a processing chamber, wherein the partial through-silicon vias formed in the substrate are blind vias, supplying an etching gas mixture including at least a fluorine containing gas and a chlorine containing gas into the processing chamber, and preferentially removing a portion of the substrate from a second surface of the substrate to expose the through-silicon vias until a desired length of the through-silicon vias is exposed from the second surface of the substrate.

Abstract translation: 本公开提供了用于通孔显示蚀刻工艺以在衬底中形成穿硅通孔（TSV）的方法。 在一个实施例中，用于执行通孔显示处理以在衬底中形成穿硅通孔的方法包括提供具有从衬底的第一表面形成到处理室中的部分穿硅通孔的衬底，其中部分通过硅 在基板上形成的通孔是盲孔，向处理室供应包含至少含氟气体和含氯气体的蚀刻气体混合物，并优先从基板的第二表面去除基板的一部分，以暴露出通孔 硅通孔直到从硅衬底的第二表面露出所需长度的通硅通孔。