公开(公告)号：US11934103B2

公开(公告)日：2024-03-19

申请号：US17668080

申请日：2022-02-09

Applicant: Applied Materials, Inc.

Inventor： Douglas A. Buchberger, Jr. ,  Dmitry Lubomirsky ,  John O. Dukovic ,  Srinivas D. Nemani

IPC: G03F7/38

CPC classification number: G03F7/38

Abstract: A method and apparatus for applying an electric field and/or a magnetic field to a photoresist layer without air gap intervention during photolithography processes is provided herein. The method and apparatus include a transfer device and a plurality of modules. The transfer device is configured to rotate a plurality of substrates between each of the modules, wherein one module includes a heating pedestal and another module includes a cooling pedestal. One module is utilized for inserting and removing the substrates from the system. At least the heating module is able to be sealed and filled with a process volume before applying the electric field.

公开(公告)号：US11815816B2

公开(公告)日：2023-11-14

申请号：US17176108

申请日：2021-02-15

Applicant: Applied Materials, Inc.

Inventor： Douglas A Buchberger, Jr. ,  Dmitry Lubomirsky ,  John O. Dukovic ,  Srinivas D. Nemani

IPC: G03F7/38

CPC classification number: G03F7/38

Abstract: A method and apparatus for applying an electric field and/or a magnetic field to a photoresist layer without air gap intervention during photolithography processes is provided herein. The method and apparatus include an electrode assembly and a base assembly. The electrode assembly includes a permeable electrode. The base assembly includes one or more process fluid channels disposed around a circumference of the substrate support surface and configured to fill a process volume with a process fluid. The electrode assembly is configured to apply an electric field to a substrate disposed within the process volume.

公开(公告)号：US11798606B2

公开(公告)日：2023-10-24

申请号：US17328491

申请日：2021-05-24

Applicant: Applied Materials, Inc.

Inventor： John O. Dukovic ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Praburam Gopalraja ,  Steven Hiloong Welch ,  Bhargav S. Citla

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

公开(公告)号：US11049537B2

公开(公告)日：2021-06-29

申请号：US16525470

申请日：2019-07-29

Applicant: Applied Materials, Inc.

Inventor： John O. Dukovic ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Praburam Gopalraja ,  Steven Hiloong Welch ,  Bhargav S. Citla

IPC: H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

公开(公告)号：US11018223B2

公开(公告)日：2021-05-25

申请号：US16502129

申请日：2019-07-03

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Nam Sung Kim ,  John O. Dukovic

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a bottom structure on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, selectively removing the second layer from the multi-material layer from the substrate, and selectively oxidizing the bottom structure on the substrate after removing the second layer from the multi-material layer.