公开(公告)号：US12204246B2

公开(公告)日：2025-01-21

申请号：US17342176

申请日：2021-06-08

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Mangesh Ashok Bangar ,  Srinivas D. Nemani ,  Steven Hiloong Welch ,  Ellie Y. Yieh ,  Dmitry Lubomirsky

IPC: G03F7/11 ,  C23C16/06 ,  G03F7/004 ,  G03F7/038 ,  G03F7/16 ,  G03F7/32 ,  G03F7/38 ,  G03F7/40

Abstract: A method for processing a substrate is described. The method includes forming a metal containing resist layer onto a substrate, patterning the metal containing resist layer, and performing a post exposure bake on the metal containing resist layer. The post exposure bake on the metal containing resist layer is a field guided post exposure bake operation and includes the use of an electric field to guide the ions or charged species within the metal containing resist layer. The field guided post exposure bake operation may be paired with a post development field guided bake operation.

公开(公告)号：US12085858B2

公开(公告)日：2024-09-10

申请号：US16825388

申请日：2020-03-20

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Srinivas D. Nemani ,  Steven Hiloong Welch ,  Mangesh Ashok Bangar ,  Ellie Y. Yieh

IPC: G03F7/20 ,  G03F7/16 ,  G03F7/38 ,  H01L21/027 ,  H01L21/266 ,  H01L21/311

CPC classification number: G03F7/20 ,  G03F7/16 ,  G03F7/38 ,  H01L21/0273 ,  H01L21/266 ,  H01L21/31133

Abstract: A method for enhancing a photoresist profile control includes applying a photoresist layer comprising a photoacid generator on an underlayer disposed on a material layer, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and drifting photoacid from the photoresist layer to a predetermined portion of the underlayer under the first portion of the photoresist layer.

公开(公告)号：US11798606B2

公开(公告)日：2023-10-24

申请号：US17328491

申请日：2021-05-24

Applicant: Applied Materials, Inc.

Inventor： John O. Dukovic ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Praburam Gopalraja ,  Steven Hiloong Welch ,  Bhargav S. Citla

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

公开(公告)号：US11049537B2

公开(公告)日：2021-06-29

申请号：US16525470

申请日：2019-07-29

Applicant: Applied Materials, Inc.

Inventor： John O. Dukovic ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Praburam Gopalraja ,  Steven Hiloong Welch ,  Bhargav S. Citla

IPC: H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10

Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.

公开(公告)号：US11880137B2

公开(公告)日：2024-01-23

申请号：US18188676

申请日：2023-03-23

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Mangesh Ashok Bangar ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Steven Hiloong Welch ,  Christopher S. Ngai

IPC: G03F7/09 ,  G03F7/20 ,  G03F7/16 ,  G03F7/11 ,  G03F7/004 ,  G03F7/039 ,  G03F7/40

CPC classification number: G03F7/094 ,  G03F7/0045 ,  G03F7/0392 ,  G03F7/11 ,  G03F7/168 ,  G03F7/203 ,  G03F7/2022 ,  G03F7/164 ,  G03F7/40

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

公开(公告)号：US11650506B2

公开(公告)日：2023-05-16

申请号：US16600101

申请日：2019-10-11

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Mangesh Bangar ,  Christopher S. Ngai ,  Srinivas D. Nemani ,  Ellie Y. Yieh ,  Steven Hiloong Welch

IPC: G03F7/11 ,  G03F7/20 ,  G03F7/09 ,  G03F7/16 ,  G03F7/40

CPC classification number: G03F7/2022 ,  G03F7/094 ,  G03F7/11 ,  G03F7/168 ,  G03F7/203 ,  G03F7/164 ,  G03F7/40

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.