公开(公告)号：US11854888B2

公开(公告)日：2023-12-26

申请号：US16908542

申请日：2020-06-22

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  Zavier Zai Yeong Tan ,  Karthik Balakrishnan ,  James S. Papanu ,  Wei-Sheng Lei

IPC: H01L21/78 ,  H01L21/67 ,  H01L21/02 ,  H01L21/268 ,  H01L21/3065

CPC classification number: H01L21/78 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/02071 ,  H01L21/268 ,  H01L21/3065

Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.

公开(公告)号：US11721583B2

公开(公告)日：2023-08-08

申请号：US16989746

申请日：2020-08-10

Applicant: Applied Materials, Inc.

Inventor： Sriskantharajah Thirunavukarasu ,  Karthik Balakrishnan ,  Karthik Elumalai ,  Eng Sheng Peh

IPC: H01L21/78 ,  H01L21/673 ,  H01L21/677 ,  B23K26/364 ,  H01L23/544 ,  B23K101/40

CPC classification number: H01L21/78 ,  B23K26/364 ,  H01L21/673 ,  H01L21/67739 ,  H01L23/544 ,  B23K2101/40 ,  H01L2223/5446

Abstract: In an embodiment, a semiconductor processing tool for implementing hybrid laser and plasma dicing of a substrate is provided. The semiconductor processing tool comprises a transfer module, where the transfer module comprises a track robot for handling the substrate, and a loadlock attached to the transfer module. In an embodiment, the loadlock comprises a linear transfer system for handling the substrate. In an embodiment, the processing tool further comprises a processing chamber attached to the loadlock, wherein the linear transfer system of the loadlock is configured to insert and remove the substrate from the processing chamber.

公开(公告)号：US20210398854A1

公开(公告)日：2021-12-23

申请号：US16908542

申请日：2020-06-22

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  Zavier Zai Yeong Tan ,  Karthik Balakrishnan ,  James S. Papanu ,  Wei-Sheng Lei

IPC: H01L21/78 ,  H01L21/67

Abstract: An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.

公开(公告)号：US20210050262A1

公开(公告)日：2021-02-18

申请号：US16539828

申请日：2019-08-13

Applicant: Applied Materials, Inc.

Inventor： Karthik Balakrishnan ,  Jungrae Park ,  Sriskantharajah Thirunavukarasu ,  Eng Sheng Peh

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67 ,  B23K26/53

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an actively-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US10784134B2

公开(公告)日：2020-09-22

申请号：US15958327

申请日：2018-04-20

Applicant: APPLIED MATERIALS, INC.

Inventor： Eng Sheng Peh ,  Karthik Balakrishnan ,  Sriskantharajah Thirunavukarasu

IPC: H01L21/67 ,  G06T7/00 ,  H01L21/677 ,  H01L21/68

Abstract: Methods and apparatus for detecting warpage in a substrate are provided herein. In some embodiments, a warpage detector for detecting warpage in substrates includes: one or more light sources to illuminate one or more substrates when present; a camera for capturing images of exposed portions of one or more substrates when present; a motion assembly having a mounting stage for supporting the camera; and a data acquisition interface (DAI) coupled to the camera to process substrate images and detect warpage of substrates based upon the processed substrate images.

公开(公告)号：US20210050263A1

公开(公告)日：2021-02-18

申请号：US16540899

申请日：2019-08-14

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  Karthik Balakrishnan ,  James S. Papanu

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L23/544 ,  H01L21/67 ,  B23K26/08 ,  B23K26/362 ,  B23K26/06

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a uniform rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US20240363412A1

公开(公告)日：2024-10-31

申请号：US18141177

申请日：2023-04-28

Applicant: Applied Materials, Inc.

Inventor： Karthik Balakrishnan ,  Zavier Tan ,  Praveen Choragudi ,  Ananth Jupudi

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67092

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a rectangular laser spot-based laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US11342226B2

公开(公告)日：2022-05-24

申请号：US16539828

申请日：2019-08-13

Applicant: Applied Materials, Inc.

Inventor： Karthik Balakrishnan ,  Jungrae Park ,  Sriskantharajah Thirunavukarasu ,  Eng Sheng Peh

IPC: H01L21/82 ,  H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/67 ,  B23K26/53

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an actively-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US10903121B1

公开(公告)日：2021-01-26

申请号：US16540899

申请日：2019-08-14

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  Karthik Balakrishnan ,  James S. Papanu

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/3065 ,  H01L23/544 ,  H01L21/67 ,  B23K26/08 ,  B23K26/362 ,  B23K26/06

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a uniform rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US11901232B2

公开(公告)日：2024-02-13

申请号：US16908537

申请日：2020-06-22

Applicant: Applied Materials, Inc.

Inventor： Karthik Balakrishnan ,  Jungrae Park ,  Zavier Zai Yeong Tan ,  Sai Abhinand ,  James S. Papanu

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/027

CPC classification number: H01L21/78 ,  H01L21/0275 ,  H01L21/3065

Abstract: Embodiments of the present disclosure include methods of determining scribing offsets in a hybrid laser scribing and plasma dicing process. In an embodiment, the method comprises forming a mask above a semiconductor wafer. In an embodiment, the semiconductor wafer comprises a plurality of dies separated from each other by streets. In an embodiment, the method further comprises patterning the mask and the semiconductor wafer with a laser scribing process. In an embodiment, the patterning provides openings in the streets. In an embodiment, the method further comprises removing the mask, and measuring scribing offsets of the openings relative to the streets.