公开(公告)号：US11637107B2

公开(公告)日：2023-04-25

申请号：US17351223

申请日：2021-06-17

申请人： Applied Materials, Inc.

发明人： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Jianxin Lei ,  Wenting Hou ,  Rongjun Wang ,  Tza-Jing Gung

IPC分类号： H01L27/108

摘要： Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

公开(公告)号：US11542589B2

公开(公告)日：2023-01-03

申请号：US16358465

申请日：2019-03-19

申请人： APPLIED MATERIALS, INC.

发明人： Rongjun Wang ,  Xiaodong Wang ,  Chao Du

IPC分类号： C23C14/14 ,  C23C14/34

摘要： Methods for depositing a dielectric oxide layer atop one or more substrates disposed in or processed through a PVD chamber are provided herein. In some embodiments, such a method includes: sputtering source material from a target assembly onto a first substrate while the source material is at a first erosion state and while providing a first amount of RF power to the target assembly to deposit a dielectric oxide layer onto a first substrate having a desired resistance-area; and subsequently sputtering source material from the target assembly onto a second substrate while the source material is at a second erosion state and while providing a second amount of RF power to the target assembly, wherein the second amount of RF power is lower than the first amount of RF power by a predetermined amount calculated to maintain the desired resistance-area.

公开(公告)号：US20220406788A1

公开(公告)日：2022-12-22

申请号：US17351223

申请日：2021-06-17

申请人： Applied Materials, Inc.

发明人： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Jianxin Lei ,  Wenting Hou ,  Rongjun Wang ,  Tza-Jing Gung

IPC分类号： H01L27/108

摘要： Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

公开(公告)号：US11251364B2

公开(公告)日：2022-02-15

申请号：US16773232

申请日：2020-01-27

申请人： Applied Materials, Inc.

发明人： Lin Xue ,  Chi Hong Ching ,  Jaesoo Ahn ,  Mahendra Pakala ,  Rongjun Wang

IPC分类号： H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  G11C11/15 ,  H01L21/768 ,  H01L45/00 ,  H01L27/24 ,  G11B5/31 ,  G11B5/39

摘要： Embodiments herein provide film stacks that include a buffer layer; a synthetic ferrimagnet (SyF) coupling layer; and a capping layer, wherein the capping layer comprises one or more layers, and wherein the capping layer, the buffer layer, the SyF coupling layer, or a combination thereof, is not fabricated from Ru.

公开(公告)号：US11081623B2

公开(公告)日：2021-08-03

申请号：US16721301

申请日：2019-12-19

申请人： Applied Materials, Inc.

发明人： Mingwei Zhu ,  Nag B. Patibandla ,  Rongjun Wang ,  Daniel Lee Diehl ,  Vivek Agrawal ,  Anantha Subramani

IPC分类号： H01L33/12 ,  H01J37/34 ,  H01L31/18 ,  H01L33/00 ,  H01J37/32 ,  H01L29/20

摘要： Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.

公开(公告)号：US10944050B2

公开(公告)日：2021-03-09

申请号：US16351850

申请日：2019-03-13

申请人： Applied Materials, Inc.

发明人： Lin Xue ,  Chi Hong Ching ,  Rongjun Wang ,  Mahendra Pakala

IPC分类号： H01L29/82 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

摘要： Embodiments of magnetic tunnel junction (MTJ) structures discussed herein employ seed layers of one or more layer of chromium (Cr), NiCr, NiFeCr, RuCr, IrCr, or CoCr, or combinations thereof. These seed layers are used in combination with one or more pinning layers, a first pinning layer in contact with the seed layer can contain a single layer of cobalt, or can contain cobalt in combination with bilayers of cobalt and platinum (Pt), iridium (Ir), nickel (Ni), or palladium (Pd), The second pinning layer can be the same composition and configuration as the first, or can be of a different composition or configuration. The MTJ stacks discussed herein maintain desirable magnetic properties subsequent to high temperature annealing.

公开(公告)号：US10236412B2

公开(公告)日：2019-03-19

申请号：US15980583

申请日：2018-05-15

申请人： Applied Materials, Inc.

发明人： Mingwei Zhu ,  Nag B. Patibandla ,  Rongjun Wang ,  Daniel Lee Diehl ,  Vivek Agrawal ,  Anantha Subramani

IPC分类号： H01L33/12 ,  H01J37/34 ,  H01L31/18 ,  H01L33/00 ,  H01J37/32 ,  H01L29/20

摘要： Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.

公开(公告)号：US10193014B2

公开(公告)日：2019-01-29

申请号：US14884251

申请日：2015-10-15

申请人： Applied Materials, Inc.

发明人： Mingwei Zhu ,  Nag B. Patibandla ,  Rongjun Wang ,  Daniel Lee Diehl ,  Vivek Agrawal ,  Anantha Subramani

IPC分类号： H01L33/00 ,  H01L33/12 ,  H01J37/34 ,  H01L31/18 ,  H01J37/32 ,  H01L29/20

摘要： Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.

公开(公告)号：US11626410B2

公开(公告)日：2023-04-11

申请号：US17861412

申请日：2022-07-11

申请人： Applied Materials, Inc.

发明人： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Jianxin Lei ,  Wenting Hou ,  Rongjun Wang ,  Tza-Jing Gung

IPC分类号： H01L27/108

摘要： Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

公开(公告)号：US20230088552A1

公开(公告)日：2023-03-23

申请号：US17478047

申请日：2021-09-17

申请人： Applied Materials, Inc.

发明人： Borui Xia ,  Anthony Chih-Tung Chan ,  Shiyu Yue ,  Wei Lei ,  Aravind Miyar Kamath ,  Mukund Sundararajan ,  Rongjun Wang ,  Adolph Miller Allen

IPC分类号： H01F7/18 ,  C23C14/35

摘要： Magnet assemblies comprising a housing with a top plate each comprising aligned openings are described. The housing has a bottom ring and an annular wall with a plurality of openings formed in the bottom ring. The top plate is on the housing and has a plurality of openings aligned with the plurality of openings in the bottom ring of the housing. The magnet assembly may also include a non-conducting base plate and/or a conductive cover plate. Methods for using the magnet assembly and magnetic field tuning are also described.